[SOLVED] How can makes delay in verilog ?

rberek said:

You would use a clocked counter to count a delay in units of the clock period. For combinatorial delay paths you would set time constraints that would put an upper bound on the delay, but that is not done in RTL.

Defining Precise delays unrelated to a clock are not possible since delays vary over process, voltage and temperature,so the synthesis tool cannot possibly put down a circuit of combinatorial components that would have a constant delay across all conditions, as is implied by the #operator in RTL.

r.b.

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rberek said:

You cannot use the # sign at all.

And 15000 what? Seconds? Microseconds? Attoseconds? Days?

r.b.

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rberek said:

No, it does not mean times. It is the number of time steps to delay. Time steps are used in simulation and are defined by the `timescale directive that would have been put somewhere in your Verilog code structure. If you have `timescale 1ns/1ns in your code, #15000 would be 15000 ns.

I ask this question because it would determine how you create this delay.

Perhaps, more importantly, what exactly is it you are trying to do? Why do you need this delay? In a proper synthesizeable digital design, there is no need to define delays in this manner. Delay times of greater than the design's clock period are done using counters or similar structures. Exact delays of less than a clock period are not possible to the best of my knowledge, for the reasons I gave in my first post.

r.b.

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