[SOLVED] How can makes delay in verilog ?

[u24c02]

Hi all

I used to # for delay in rtl simulation,

But that # is not work in synthesis.

So how can i make delay time processing like as # in synthesis code?

 

[rberek]

You would use a clocked counter to count a delay in units of the clock period. For combinatorial delay paths you would set time constraints that would put an upper bound on the delay, but that is not done in RTL.

Defining Precise delays unrelated to a clock are not possible since delays vary over process, voltage and temperature,so the synthesis tool cannot possibly put down a circuit of combinatorial components that would have a constant delay across all conditions, as is implied by the #operator in RTL.

r.b.

 

[u24c02]

You would use a clocked counter to count a delay in units of the clock period. For combinatorial delay paths you would set time constraints that would put an upper bound on the delay, but that is not done in RTL.

Defining Precise delays unrelated to a clock are not possible since delays vary over process, voltage and temperature,so the synthesis tool cannot possibly put down a circuit of combinatorial components that would have a constant delay across all conditions, as is implied by the #operator in RTL.

r.b.

you mean i have to make counter block then use like delay syntax ?(#)
Is there any other way?

i have to use delay syntax 15000.

 

[rberek]

You cannot use the # sign at all.

And 15000 what? Seconds? Microseconds? Attoseconds? Days?

r.b.

 

[u24c02]

You cannot use the # sign at all.

And 15000 what? Seconds? Microseconds? Attoseconds? Days?

r.b.

Yes i know that i can not use # in synthesis.
So i need alternative way.

15000 means times. That is, so many delay # Is needed in my design after synthesis

 

[rberek]

No, it does not mean times. It is the number of time steps to delay. Time steps are used in simulation and are defined by the `timescale directive that would have been put somewhere in your Verilog code structure. If you have `timescale 1ns/1ns in your code, #15000 would be 15000 ns.

I ask this question because it would determine how you create this delay.

Perhaps, more importantly, what exactly is it you are trying to do? Why do you need this delay? In a proper synthesizeable digital design, there is no need to define delays in this manner. Delay times of greater than the design's clock period are done using counters or similar structures. Exact delays of less than a clock period are not possible to the best of my knowledge, for the reasons I gave in my first post.

r.b.

 

[u24c02]

No, it does not mean times. It is the number of time steps to delay. Time steps are used in simulation and are defined by the `timescale directive that would have been put somewhere in your Verilog code structure. If you have `timescale 1ns/1ns in your code, #15000 would be 15000 ns.

I ask this question because it would determine how you create this delay.

Perhaps, more importantly, what exactly is it you are trying to do? Why do you need this delay? In a proper synthesizeable digital design, there is no need to define delays in this manner. Delay times of greater than the design's clock period are done using counters or similar structures. Exact delays of less than a clock period are not possible to the best of my knowledge, for the reasons I gave in my first post.

r.b.

Sorry about that i use some miss words
I mean that when i use time scale like 1ns/1ps, #1 is working delay for 1ns.
But i can't get in synthesis net. So i asking any other way in synthesis netlist.

And i mean that 15000 is not delay time but count of used # delay in verilog.
So i want to know how can i get to apply delay #1 in synthesis netlist.

I want use SDF from synopsys STA to my xilinx ise bit file.

But i can not think any others way to supply SDF to xilinx bit file