darkslate
Junior Member level 1
I have two modules in my design.
one module dut1 uses asic libraries , the other dut2 uses xilinx coregen libraries.
the problem is that I want +delay_mode_zero complie option in dut1,
and not in dut2.
so I compiled as the followings.
ncverilog dut1.v +delay_mode_zero
ncverilog dut2
but when I compile dut2, it didn't find the dut1 instance in the library
how can I solve this.
In modelsim, I works find.
please help me......
one module dut1 uses asic libraries , the other dut2 uses xilinx coregen libraries.
the problem is that I want +delay_mode_zero complie option in dut1,
and not in dut2.
so I compiled as the followings.
ncverilog dut1.v +delay_mode_zero
ncverilog dut2
but when I compile dut2, it didn't find the dut1 instance in the library
how can I solve this.
In modelsim, I works find.
please help me......