You've got a part with 484 TOTAL pins, many of which are dedicated to power, etc. Again, you can't use more pins than you have.
Is this your first FPGA design?
Maybe you should start with a simpler project...
if you have a dev board, you should never run out of io pins because you know what IO you have available and shouldn't make choices that would use other IO's.
If this is your first FPGA design, you should clarify what your goals are. In FPGA designs, the top level ports are connected to IO's, and many tools will try to auto-connect IOBs if you don't specify where they should be placed. This is actually a very bad default choice, but it is what vendors have chosen.
I suspect you have a design that you've simulated, and that had several ports. When you chose synthesis, it tried to assign these top level ports to IO pins.
Check to see how to disable IO insertion if you are just trying to see how the logic maps to the FPGA internals. If you want a practical design, select the IOs to match what is on your dev board. If you are designing a new board, you would need to move to a bigger FPGA or change your IO.
FPGAs are not software, they are hardware; don't make the mistake of equating VHDL with a programming language like C. You are creating hardware, NOT SOFTWARE. I can not emphasize this enough to new FPGA users.
You can simulate if you want, but since hardware is completely deterministic you should be able to determine how long it takes to run a process if you understand your hardware. It is totally dependent on number of clock cycles and, thus, clock frequency.
I don't understand that statement "maybe sth can be".
if you have a dev board, you should never run out of io pins because you know what IO you have available and shouldn't make choices that would use other IO's.
If this is your first FPGA design, you should clarify what your goals are. In FPGA designs, the top level ports are connected to IO's, and many tools will try to auto-connect IOBs if you don't specify where they should be placed. This is actually a very bad default choice, but it is what vendors have chosen.
I suspect you have a design that you've simulated, and that had several ports. When you chose synthesis, it tried to assign these top level ports to IO pins.
Check to see how to disable IO insertion if you are just trying to see how the logic maps to the FPGA internals. If you want a practical design, select the IOs to match what is on your dev board. If you are designing a new board, you would need to move to a bigger FPGA or change your IO.
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