viviwei
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Hi, gurus:
I'm a newbie in EDA feild. Now I have to implement a iic controller which only supporting master & transmit mode.
I use the Xilinx & synplify pro 7.6 and ModelSim 5.8 to simulate and synthese. And it can be done successfully. But when going to Implimetion, some error will be encounted.Here r them:
ERROR:Map:6 - Bad format for RLOC constraint "X0Y0" on FDCE symbol
ERROR:Map:6 - Bad format for RLOC constraint "X0Y0" on FDCE symbol
ERROR:Map:52 - Problem encountered processing RPMs.
How can I do?
I'm a newbie in EDA feild. Now I have to implement a iic controller which only supporting master & transmit mode.
I use the Xilinx & synplify pro 7.6 and ModelSim 5.8 to simulate and synthese. And it can be done successfully. But when going to Implimetion, some error will be encounted.Here r them:
ERROR:Map:6 - Bad format for RLOC constraint "X0Y0" on FDCE symbol
ERROR:Map:6 - Bad format for RLOC constraint "X0Y0" on FDCE symbol
ERROR:Map:52 - Problem encountered processing RPMs.
How can I do?