Collang2
Junior Member level 3
I'm studying two EDA tools, and I want to know more about how to remove negative slacks.
I tried timing optimization with 'group and ungroup', and using 'compile_ultra' command.
And I understand that we can divide the DAT using the pipeline or insert a buffer to increase the DAT, but can we do this in DC?
1. What are some of the representative ways to reduce slack(Setup and hold) in Desing Compiler and Prime time?
DC :
PT :
2. Can I design the pipeline and insert buffer in DC(without changing the RTL code)?
3. Can't I improve my slacks at Prime time?
I tried timing optimization with 'group and ungroup', and using 'compile_ultra' command.
And I understand that we can divide the DAT using the pipeline or insert a buffer to increase the DAT, but can we do this in DC?
1. What are some of the representative ways to reduce slack(Setup and hold) in Desing Compiler and Prime time?
DC :
PT :
2. Can I design the pipeline and insert buffer in DC(without changing the RTL code)?
3. Can't I improve my slacks at Prime time?