How can I make up .vcd file directly?

zpmanr · Dec 17, 2004

$fdumpfile

Generally we simulate according to following steps in Modelsim:
1.compile design code & testbench;
2.special the corresponding .sdf file ;
3.excute .do file which includes "force" section;
4.view waveform.

How can I dump waveform to vcd file through up steps directly?
And how can I dump waveform to fsdb file directly?

Thanks a lot!!

ukapil · Dec 21, 2004

make vcd from dump

In verilog include the following in the testbench.

initial
begin
$dumpvars();
$fdumpfile ("./dump.vcd");
#10000 $finish;
end

let me know if this works out.

--kapil

wadaye · Dec 22, 2004

dump vcd

zpmanr said:
Generally we simulate according to following steps in Modelsim:
1.compile design code & testbench;
2.special the corresponding .sdf file ;
3.excute .do file which includes "force" section;
4.view waveform.

How can I dump waveform to vcd file through up steps directly?
And how can I dump waveform to fsdb file directly?

Thanks a lot!!

Hi zpmanr,

You need some variable setting and a PLI file from novas to dump fsdb file directly, you can find detail info in the reference of Debussy or Verdi.

wang1

How can I make up .vcd file directly?

zpmanr

Newbie level 5

ukapil

Member level 2

wadaye

Full Member level 4

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How can I make up .vcd file directly?

zpmanr

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