How can I make up .vcd file directly?

[zpmanr]

$fdumpfile

Generally we simulate according to following steps in Modelsim:
1.compile design code & testbench;
2.special the corresponding .sdf file ;
3.excute .do file which includes "force" section;
4.view waveform.

How can I dump waveform to vcd file through up steps directly?
And how can I dump waveform to fsdb file directly?

Thanks a lot!!

 

[ukapil]

make vcd from dump

In verilog include the following in the testbench.

initial
begin
$dumpvars();
$fdumpfile ("./dump.vcd");
#10000 $finish;
end


let me know if this works out.

--kapil

 

[wadaye]

dump vcd

Generally we simulate according to following steps in Modelsim:
1.compile design code & testbench;
2.special the corresponding .sdf file ;
3.excute .do file which includes "force" section;
4.view waveform.

How can I dump waveform to vcd file through up steps directly?
And how can I dump waveform to fsdb file directly?

Thanks a lot!!

Hi zpmanr,

You need some variable setting and a PLI file from novas to dump fsdb file directly, you can find detail info in the reference of Debussy or Verdi.

wang1