How can I know the maximum speed of an IP

I have a free core for 8051, I want to know the maximum frequency that the IP can operat with. I sent a time constraint to the desired frequency and the synthesizer (Le@n@rdo) gave negative slacks, but this -ve slack may be due to I did not set the multicycles pathes and to know that I should go through the VHDL code to understand the detailed construction of the IP (which is time consuming and violat the benifite of IP idea). does any one pass through this dilema before and what is the suggested solutions.

If it is a free core, chances are it is not optimized for the Device Architecture you are targeting to. And this is very important for FPGAs. I dont think you can get aaway with out changing the VHDL. It all depends on how bad your slack is. And if you can look through the paths that have negative slack, check for the following.

1) Too many levels of logic
2) High Fanout Nets
and maybe some other features

If you find these sometimes you can fix by using constraints in your front end/back end tools. For starters you can ask Leonardo to optimize your design for Area instead of speed. You can also try Logic Replication, and floor plannning. But these efforts also require time and expertise. It all depends on your case.

Another thing to note is Leonardo may not give you any slack. That doesnt mean the backend place&route will also meet timing.

Or, you can try using a faster grade part .. That is the only quick fix.

Hope this helps
Kode

Check place and route. If it works go ahead ow change the contraint

The real issue Farouk is asking about is how to identify multicycle path without investigating the code. It is an interesting topic. But from what i know, there is no tools that is smart enough to do this. Normally the IP provider would have this information.

regards

Check to see if anyone else tried to port the free core you are using for your target Device. Maybe they have gone thru this kinda thing.
May be the OP should have mentioned the device he is targeting?

I have missed the multicyple path question. There is a tool that does exactly what we all want - a tool that auto identifies these multicycle, false paths so when you run P&R you are only trying to close timing on the real constraints of the design. Atleast thats what the company claims. You can look up their webpage for more information https://www.fishtail-da.com/

The big application target is when individuals who were NOT the
RTL designers and may not know their way around the code do the P&R. The tools can work and identify most of these issues, so handlers of "blind" netlist blocks are not spending most of their time on un-real things.

Alternatively, if you find these multicycle paths manually, you can export the Multicycle paths constraints to your P&R from Leonardo using the TCL scripting capability.

Another suggestion, is to see if you can turn on Pipelining options in your synthesis tool and meet timing. This most likely aint gona cut it. It wouldnt hurt to try.

Kode