william_luo
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Hi, there.
I want to create a verilog netlist for a schematic (cadence virtuoso, version 6.1.5). From a tutorial I found online, it seems that I can do this by Verilog-XL. The tutorial shows me that selecting Tools->Simulation->Verilog-XL can invoke the "setup environment" window, but I can't find the Verilog-XL option at all according to those steps. Then, I can only see the option of NC-Verilog and I know that they are different.
So how can I use the Verilog-XL for the netlist thing by this version of virtuoso?
Thanks a lot!
I want to create a verilog netlist for a schematic (cadence virtuoso, version 6.1.5). From a tutorial I found online, it seems that I can do this by Verilog-XL. The tutorial shows me that selecting Tools->Simulation->Verilog-XL can invoke the "setup environment" window, but I can't find the Verilog-XL option at all according to those steps. Then, I can only see the option of NC-Verilog and I know that they are different.
So how can I use the Verilog-XL for the netlist thing by this version of virtuoso?
Thanks a lot!