How about the delay cell control voltage. I mean normally , V control will be added
to delay cell through a source follow. The source of this source follow is the acturally control voltage of your delay cells.Suppose your control voltage noise
is 1mv(base on your pic) , the the frequency variation will be 500KHz, so the output frequency will be ,let say, 200.5Mhz.
The peak to peak jitter of clock will be 5n- 4.987n=13p. That is small compare to
other noise source.