[SOLVED] How can I hide the netlist in a symbol?

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CMOS-Tangram

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Hi to all!

I have been designing an amplifier + Test Buffer (50 Ohm) for a company and now I have to send my first results. This design has been developed in cadence.

My question is:

Is there any way to create a symbol that reproduces the circuit behavior but hides the netlist?

Greetings and thanks in advance!
 

Yes - if you can create a behavioural model in Verilog-A or AVHDL .
 

Thank you very much erikl!

But I have a schematic/layout design, I think that I can not create a Verilog-A model from the schematic/layout-extracted. Is there another solution?

Greetings and thanks in advance!
 

CMOS-Tangram said:
... I have a schematic/layout design, I think that I can not create a Verilog-A model from the schematic/layout-extracted. Is there another solution?
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I don't think so. If you'd know how to write a behavioural model in Verilog-A (or AHDL) you could only send the corresponding symbol together with its behavioural description. But if you have to send the layout, the netlist could be extracted anyway.
 

At the end I used this solution:

Extract the circuit netlist and then using the command spectre_encrypt hide/encrypt the content of the netlist.

Greetings and thanks for all.
 
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