You really need to go read a book firstly on digital logic design (Paying particular attention to the words synchronous and combinatorial), then on VHDL, EVERYTHING is concurrent unless you force it to not be.
The keyword is pipelining, create an entity containing your preprocessing logic, register the output and then hook it to your main processing blocks, you may wish to provide a 'data valid' strobe to the processing blocks from the preprocessor.
At any given time the preprocessor logic is computing the data to be handed off to the processing blocks on the rising edge of the NEXT clock pulse, while at the same time the processing blocks are calculating outputs based on the output of the preprocessor which changed at the last rising edge of the clock.
This is very, very standard stuff.
Regards, Dan.