How can I geta hierarchical post P&R netlist in Xilinx I

[wkong_zhu]

How can I write hierarchical post simulation netlist in ISE.

I clicked the "keep hierarchical" option in translate step, and clicked the " hierarchical" option in P&R step., But still write a single module verilog
file.

The EDF input is hierarchical, But the Post P&R netlist is always a flattened single module.

How can I get a hierarchical netlist.

 

[masai_mara]

Re: How can I geta hierarchical post P&R netlist in Xili

In the synthesize option in the process view you right click, goto properties and in synthesis options you select keep hierarchy. I guess this is avialable in ISE6.3

Added after 1 hours 25 minutes:

apparently you can also use the synthesis attributes to specify the retention of hierarchy. For vhdl it is

architecture hier of abc is
--in architecture declaration region
attribute keep_hierarchy: string;
begin
--in architecture body
attribute keep_hierarchy of hier : architecture is yes/no/soft(choose yes);
--

this can be used for any other veraions of ise also.

 

[wkong_zhu]

I use DC-FPGA for synthesis, the EDF file is hierarchical.
How can I maintain the hierarchy.