How can i get the corresponding binary values to every character that read from file?

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spandana51

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I have written a code to read text and to write the same text to the other text file and i want to convert each character read from the input text to an corresponding binary value. And the reading and writing text perfectly worked but the problem is it is showing only the value corresponding to the first character in the text. Please give me the idea where i am doing the mistake. Here's my code:
Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity asconvbin is
    Port ( clk : in  STD_LOGIC;
           d : out  STD_LOGIC_VECTOR(7 downto 0));
              
end asconvbin;
 
architecture Behavioral of asconvbin is
 
begin
process(clk)
 variable OUTLINE : LINE;
      file FILEOUT : TEXT is OUT "outputfile.txt";
   
      --Input variables
            variable inline:line;
            variable char:character; 
            variable end_of_line:boolean;
            file myfile:text is "myfile.txt";
        variable k:integer;
begin
if rising_edge(clk) then
  
    while not endfile(myfile) loop
       readline(myfile,inline);     
         k:=inline'high;
 
        end_of_line := true;
        while end_of_line loop
         read(inline,char,end_of_line);
          
for i in k downto 0 loop
 
if char='A' then d<="01000000";
elsif char='B' then d<="01000001";
elsif char='C' then d<="01000010";
elsif char='D' then d<="01000011";
elsif char='E' then d<="01000100";
elsif char='F' then d<="01000101";
elsif char='G' then d<="01000110";
elsif char='H' then d<="01000111";
elsif char='I' then d<="01001000";
elsif char='J' then d<="01001001";
elsif char='K' then d<="01001010";
elsif char='L' then d<="01001011";
elsif char='M' then d<="01001100";
elsif char='N' then d<="01001101";
elsif char='O' then d<="01001110";
elsif char='P' then d<="01001111";
elsif char='Q' then d<="01010000";
elsif char='R' then d<="01010001";
elsif char='S' then d<="01010010";
elsif char='T' then d<="01010011";
elsif char='U' then d<="01010100";
elsif char='V' then d<="01010101";
elsif char='W' then d<="01010110";
elsif char='X' then d<="01010111";
elsif char='Y' then d<="01011000";
elsif char='Z' then d<="01011001";
else null;
            
             end if;
             k:=k-1;
end loop;
 
     if end_of_line then 
            WRITE(OUTLINE,char);
          end if;
    end loop;
end loop;
WRITELINE(FILEOUT, OUTLINE); --writes outline variable to file.
 
--end loop;
end if;
end process;
 
end Behavioral;
 
Last edited by a moderator:

This is because you are assigning D multiple times in the same clock cycle, starting with the last value on the line and ending with the first. So the last assignment (which is the first character) overrides all the other assignments.

Some other notes:
1. You code reads the entire file on every clock cycle, and outputs the file with \n chars removed.
2. You're using '87 file syntax. You really should use '93:

Code VHDL - [expand]
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file myfile:text open read_mode is "myfile.txt";
file FILEOUT : TEXT open write_mode is "outputfile.txt";


3. What are these D values? they are 1 less than the real ascii value. You could have done this instead of the case statement:

Code VHDL - [expand]
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use ieee.numeric_std.all;
 
....
 
d <= std_logic_vector( to_unsigned( character'pos(char), 8 ) );



So, what are you actually trying to do?
 

i want to read a text from a file and have to get the corresponding ascii value to the read character for every clock cycle. yeah i will change that ascii value.
 

First : I assume you realise this is just simulation code - none of this is synthesisable.

If you only want to play out a single character on each clock cycle, then it would be easier just to open the file at the beginning of the sim and either read 1 char per clock or dump the whole file into a constant array at initialisation time (using an initialisation function to read the file) and then just indexing to the appropriate char.
 

spandana51 said:
No, i need the program to be synthesisable.
Click to expand...
The real problem you are having is treating VHDL as if it was software. VHDL is a hardware decription language.
Think about it...how is your synthesized design loaded into an FPGA on a board supposed to get the file off your HDD and onvert said file into binary?
 

spandana51 said:
No, i need the program to be synthesisable.
Click to expand...

Then you need a whole different approach.
You probably want a rom pre-loaded with a load of values, that you read out using a counter as the address. This would be a first step, before moving on to something like a UART to receive data from a PC.

Basically, none of the current code is usable.
 
It is a part of my encryption system. I have written the code for encrypting the data so that my system can accept any num of bits that are transmitted serially. But i want to give the text as input then converting those characters into binary. That is why i have proceeded with the above method. And am not implementing it on FPGA rather than i am going to optimize the design using SoC encounter.
 

And how is using encounter much different than targeting an FPGA? It still translates RTL to hardware circuits. And a file i/o operation can't be synthesized into hardware. As tricky already stated you have to either use a ROM or if the data has to be changed use a UART or some other standard interface protocol with the host that has the file data you are encrypting.

I think besides not understanding VHDL being a hardware description language, you also need to understand how to do a system design.
 

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