How can I get GigE packet?

Hi all:

I have a altera DE2-115 platform.

The platform have 2 ethernet port and 2 88E1111 IC.

Can I use this platform to get GigE packet and data?

How can I to do?

Somebody can give me suggestion or direction?

Very thanks.

Step1:
look at theDE2-115 documentation, schematics, and example designs. It is possible there is an example design that contains most or all of the IP you want to use.

Step2:
determine which of the 88E1111 modes are possible with the DE2-115. eg, GMII, RGMII, SGMII, etc... For RGMII, read to see if the required clock delays are done on-board already. RGMII requires delays on the TXC/RXC. In modern times both PHY and FPGA can accomplish these functions, but it is important not to do this on both.

Step3:
Determine if you need MDIO access to the PHY, and if so which registers to set. The 88E1111 doesn't have a public data sheet, however the main registers are defined in the linux kernel modules. You can read some of the C code to figure out which addresses are useful to you.

Step4: if you can't use an example design, check to see what IP is available to you from altera or other sources. you are looking for at least an EMAC (GEMAC/TEMAC) that supports 1Gbe.

Step5: At this point, you would have to find IP or write IP to do the specific packet functions you need. This likely means a simple UDP/IP stack.

I try the ethernet demo project.

It's seems to program a microC/OS in DE2-115.

Can I get GigE data in nonOS system?

With a Cyclone it is unlikely to get a GigE bandwidth filled with a soft core system and OS. I did this on NIOS recently and found strong limilations. To drive Ethernet with nearly 1000Mbit a small FPGA core is required.

You can easily calculate yourself that through the given 8Bit data width in (R)GMII, you will need 125MHz clock speed with a more or less 100% filled buffer to transmit at GigaSpeed.

fpgaengineer said:

With a Cyclone it is unlikely to get a GigE bandwidth filled with a soft core system and OS. I did this on NIOS recently and found strong limilations. To drive Ethernet with nearly 1000Mbit a small FPGA core is required.

You can easily calculate yourself that through the given 8Bit data width in (R)GMII, you will need 125MHz clock speed with a more or less 100% filled buffer to transmit at GigaSpeed.

Click to expand...

Hi,
can you please explain or share the c application that you have did for Nios MDIO interface ?

i want to know how we can read and write and we need to set some address initially .. can you share those details

i got some picee of code

pls see
alt_u32 t2=0;

IOWR_ALTERA_TSEMAC_MDIO_ADDR1(TRIPLE_SPEED_ETHERNET_0_BASE, 0); // PHY and other board peripheral initialization
IOWR_ALTERA_TSEMAC_MDIO_ADDR0(TRIPLE_SPEED_ETHERNET_0_BASE, PHY);
do
{
// Control Register .15 = 1 - Reset
IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 0, 0x8000);
Delay(0xFFFF);
// (.13=0, .6=1) - 1000 Mbps, .12=1 - Enable Auto-Negatiation,
IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 0, 0x1040);
Delay(0xFFFF);
// read Control Register
t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 1);
Delay(0xFFFF);
// Control Register .15 = 1 - Reset
IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 0, t2 | 0x8000);
Delay(0xFFFF);
// read Staus Register
t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 1);
alt_printf("Reg 1 : %x\n",t2);
//check Link
if( (t2&0x0004)==0 )
{
// Control Register .15 = 1 - Reset
IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 0, t2 | 0x8000);
Delay(0xFFFF);
}
// .15=1 - Copper, (.3:.0)='0100' - SGMII without Clock with SGMII Auto-Neg to copper
IOWR_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 27, 0x8004);
Delay(0xFFFF);
// read Staus Register
t2 = IORD_ALTERA_TSEMAC_MDIO(TRIPLE_SPEED_ETHERNET_0_BASE, 0, 1);
alt_printf("Reg 1 : %x\n",t2);
}
while( (t2&0x0004)==0 );