How can I get 2M CLK signal from 19.44M Overhead signal?

2.048m to 19.44m pll

It's my the first time been here , so nice to meet all of you. ^_^

I am now using Xilinx Spantan 2E ,
What I had in hand is 19.44M Overhead signal (from other linecard),
and all I need is to get 2M CLK signal from it,
How can I do it?
Tell me how you think about it.

I would appriecate your help very much if you can give out
the Verilog code for this problem.

Hi predator,

Welcome then

How accurate do you want your 2M clock? If is not very accurate you can get a 1.944 MHz clock just dividing by 10 8)
How many clocks have you got available on your FPGA and what are their frequencies?

Regards,

-maestor

phase jitter

If you do not mind a lot of phase jitter, you can divide by 10 part of the time and 9 the other part in whatever ratio that brings you to the average frequency of 2M.

Thank you , maestor and flatulent.

What I need is 2.048M CLK signal to be exact.

Any suggestion?

i think you are working with the STM1 project!
you must use a PLL to generate 2.048M from the 19.44M

regards

do you working in STM1 project! if yes, 2.048Mbps is the standard rate of E1 stream

to hienpv:

How smart you are!

Hi Predator,

You can design a digital PLL in FPGA with 8K reference input as well as a 32.768M master clock. The 8K clock can be derived from overhead signal. If you want to meet the jitter requirement of ITU-T, you need to double the master clock and then use both edges to lock to the reference.

yes, i think you can deriving clock 8k from A1A2 byte!

Why do you want to generate a 2.048M clock?
What is your STM1 frame carrying? E1 data? because you could extract the E1 clock from the data...

Hi Davis, could you explain further how to get an E1 clock and meet the jitter specs. using a 19.44MHz and the A1A2 bytes?

So predator...have you get any more clocks?

Take care,
-maestor

The jitter is more important for transmission, using 19M to get 2M will not meet the requirement of G.703 . using extern PLL to get 2M from 8k,which is may be divided from 19M, is the most popular solution .

Hi Maestor,

Jitter is measured as the position offset comparing to an ideal clock edge. To make a PLL design meet the jitter spec., you need to distribute each adjustment opportunity as uniformly as possible and minimize each adjustment offset at the same time.

Thanks for the answer Davis,

But what I don't understand yet is the way you suggested to predator

You can design a digital PLL in FPGA with 8K reference input as well as a 32.768M master clock. The 8K clock can be derived from overhead signal. If you want to meet the jitter requirement of ITU-T, you need to double the master clock and then use both edges to lock to the reference.

I'll try to work it out when I have some time or feel free to explain further,

-maestor

I advise you to review the division ratios that can be provided by the DLL. I think it is the most suitable solution to get accurate 2.048 clock.

Davis said:

Hi Predator,

You can design a digital PLL in FPGA with 8K reference input as well as a 32.768M master clock. The 8K clock can be derived from overhead signal. If you want to meet the jitter requirement of ITU-T, you need to double the master clock and then use both edges to lock to the reference.

Click to expand...

Can anyone tell me why the master clock must be doubled(to 65.536M)? How can I estimate the jitter characteristics of E1 interface? and what is the relationship of the master clock frequency and E1 jitter character?

Thanks in advance.

anybody tell me? please!

Hi all. There is obviously no way derive a clean, jitter-compliant 2.048MHz clock from a 19.44MHz clock in the digital domain. You need an external PLL.

However, if you think about what you need the clock for then it may turn out that you don't need actually need it. For example, if your application is an STM1-> E1 demux (ie: it takes an STM1 in and transmits 63 E1s out) then there are other solutions. It may seem that you need a 2.048MHz clock to drive the E1 LIUs, but newer LIUs from the likes of IDT have internal jitter attenuators which meen you can clock transmit data into them at a faster "gapped" clock, and the LIU takes care of generating the clean 2.048MHz data stream. "Gapping" the clock down to an effective 2.048MHz data rate is something that is easyily done in the digital domain, without resorting to external PLLs.

A second scenario - if the 2.048MHz clock is only to be used internally to the FPGA then I'd run that circuitry at 19.44MHz, but "chip-enable" it down to an effective 2.048MHz. The "chip-enable" can be derived from a DDS, which will give an accurate long-term 2.048MHz rate, but be very jittery.

However, if you really need to drive a clean 2.048MHz clock out of your FPGA then I think you'll need the external PLL...

J

and in response to Davis - if there is already a 32.768MHz clock available then there is no need for any DLL/PLL or clever digital circuitry. Divide by 16 (only takes a few flip-flops) and you have your 2.048MHz clock. I assume this query arises because there is no easy multiple of 2.048MHz available in the system...

Check out this, it may help you

Hi:
Basically a DPLL will required to perform the task.
If you use FPGA or CPLD to do the diving you have to be very careful on the O/P jitter.

If you can accept the external device, ICST, IDT and Semtech has such devices that you can use.