How can I fix this error?

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Darrow.strath

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I have the error in my VHDL design project:
[XSIM 43-3249] File C:/Users/hp/Desktop/correct_file_WTB/correct_file_WTB/project/project.srcs/sources_1/new/Sports_venue.vhd, line 53. Unresolved signal "dec" is multiply driven.
Click to expand...

So I know that it has something to do with that there are two instances that are driving this decimal signal but I am confused as I thought I only have one instance driving it, I'd appreciate it if someone can spot the point of the error and fill me in on how to fix it.

Edit: sorry should probably explain what I'm trying to achieve as well, I'm making a system that will have 12 counters that will count up and down everyone who enters or leaves a stadium during some sports event, and then an adder adds all those outputs up together and displays them on 4 7-segment displays (one for each digit), the problem is with our "dec" standing for decimal, we want to add up all those counter outputs and convert them into a decimal value and then it gets converted to 4 4-bit binary numbers that will go to each 7-seg display, these numbers match the truth table for a 7-seg decoder to display the correct numbers.

Sports_venue.vhd:

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values


-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Sports_venue is
  Port(enable_in, reset_in, updown_in : in std_logic_vector(0 to 11);
           seg_1, seg_2, seg_3, seg_4 : out std_logic_vector(3 downto 0));
end Sports_venue;

architecture Behavioral of Sports_venue is

type counter_output is array (positive range <>) of unsigned (7 downto 0);

component counter
    port(CLK, enable, reset, updown : in std_logic;
                          Q : out unsigned(7 downto 0));
end component;


signal enable, reset, updown : std_logic_vector(1 to 12);
signal CLK_TB : std_logic;
signal adder_input : counter_output(1 to 12);
signal add_output : unsigned(11 downto 0);
signal dec, z : integer;

begin

CLK_loop : process
    begin
        while now <= 3000ns loop
            CLK_TB <= '1';
            wait for 5 ns;
            CLK_TB <= '0';
            wait for 5 ns;  
        end loop;
        wait;
    end process;



add_output <= unsigned(adder_input(12) + adder_input(1) + adder_input(2) + adder_input(3)
+ adder_input(4) + adder_input(5)+ adder_input(6) + adder_input(7) + adder_input(8)
+ adder_input(9) + adder_input(10) + adder_input(11));

dec <= to_integer(add_output);


   seg_1_loop : process(dec)
   begin
    case dec is
        when 0 to 999 => z <= 0;
        when 1000 to 1999 => z <= 1;
        when 2000 to 2999 => z <= 2;
        when 3000 => z <= 3;
        when others => z <= 0;
   end case;
     if( z = 0) then
        seg_1 <= "0000";
     elsif( z = 1) then
        dec <= dec  - 1000;
        seg_1 <= "0001";
     elsif(z = 2) then
        dec <= dec - 2000;
        seg_1 <= "0010";
     elsif(z = 3) then
        dec <= dec - 3000;
        seg_1 <= "0011";
   end if;
   end process;
   
seg_2_loop : process(dec)
   begin
    case dec is
        when 0 to 99 => z <= 0;
        when 100 to 199 => z <= 1;
        when 200 to 299 => z <= 2;
        when 300 to 399 => z <= 3;
        when 400 to 499 => z <= 4;
        when 500 to 599 => z <= 5;
        when 600 to 699 => z <= 6;
        when 700 to 799 => z <= 7;
        when 800 to 899 => z <= 8;
        when 900 to 999 => z <= 9;
        when others=> z <= 0;
    end case;
    if(z = 0) then
        seg_2 <= "0000";
   elsif(z = 1) then
            dec <= dec  - 100;
            seg_2 <= "0001";
   elsif (z = 2) then
            dec <= dec - 200;
            seg_2 <= "0010";
   elsif(z = 3) then
            dec <= dec - 300;
            seg_2 <= "0011";
   elsif (z = 4) then
            dec <= dec - 400;
            seg_2 <= "0100";
   elsif (z = 5) then
            dec <= dec - 500;
            seg_2 <= "0101";
   elsif (z = 6) then
            dec <= dec - 600;
            seg_2 <= "0110";
   elsif (z = 7) then
            dec <= dec - 700;
            seg_2 <= "0111";
   elsif (z = 8) then
            dec <= dec - 800;
            seg_2 <= "1000";
   elsif (z = 9) then
            dec <= dec - 90;
            seg_2 <= "1001";
   end if;
end process;

seg_3_4_loop : process(dec)
   begin
    case dec is
        when 0 to 9 => z <= 0;
        when 10 to 19 => z <= 1;
        when 20 to 29 => z <= 2;
        when 30 to 39 => z <= 3;
        when 40 to 49 => z <= 4;
        when 50 to 59 => z <= 5;
        when 60 to 69 => z <= 6;
        when 70 to 79 => z <= 7;
        when 80 to 89 => z <= 8;
        when 90 to 99 => z <= 9;
        when others=> z <= 0;
    end case;
            if( z = 0) then
            dec <= dec  - 10;
            seg_3 <= "0000";
   elsif (z = 1) then
            dec <= dec - 20;
            seg_3 <= "0001";
   elsif (z = 2) then
            dec <= dec - 30;
            seg_3 <= "0010";
   elsif (z = 3) then
            dec <= dec - 40;
            seg_3 <= "0011";
   elsif (z = 4) then
            dec <= dec - 50;
            seg_3 <= "0100";
   elsif (z = 5) then
            dec <= dec - 60;
            seg_3 <= "0101";
   elsif (z = 6) then
            dec <= dec - 70;
            seg_3 <= "0110";
   elsif (z = 7) then
            dec <= dec - 80;
            seg_3 <= "0111";
   elsif (z = 8) then
            dec <= dec - 90;
            seg_3 <= "1000";
               elsif (z = 9) then
            dec <= dec - 90;
            seg_3 <= "1001";
   end if;
seg_4 <= std_logic_vector(to_unsigned(z, seg_4'length));
end process;

counter_gen:
    for i in 1 to 12 generate
        counterX: counter
         port map (CLK => CLK_TB, enable => enable(i), reset => reset(i), updown => updown(i), Q => adder_input(i));
    end generate;
end Behavioral;
 
Last edited by a moderator:

you are assigning dec outside the process

dec <= to_integer(add_output)

as well as inside the process.
 
barry said:
you are assigning dec outside the process

dec <= to_integer(add_output)

as well as inside the process.
Click to expand...

thanks, My solutions was going to be to make more integers called: thousands, hundreds, tens and ones, and the dec's inside the process will be changed to their respective integers.

Code: 
signal dec, z, thousands, hundreds, tens, ones : integer;

seg_2_loop : process(dec)
   begin
    case hundreds is
        when 0 to 99 => z <= 0;
        when 100 to 199 => z <= 1;
        when 200 to 299 => z <= 2;
        when 300 to 399 => z <= 3;
        when 400 to 499 => z <= 4;
        when 500 to 599 => z <= 5;
        when 600 to 699 => z <= 6;
        when 700 to 799 => z <= 7;
        when 800 to 899 => z <= 8;
        when 900 to 999 => z <= 9;
        when others=> z <= 0;
    end case;
    if(z = 0) then
        seg_2 <= "0000";
   elsif(z = 1) then
            hundreds <= thousands  - 100;
            seg_2 <= "0001";
   elsif (z = 2) then
            hundreds <= thousands - 200;
            seg_2 <= "0010";
   elsif(z = 3) then
            hundreds <= thousands - 300;
            seg_2 <= "0011";
   elsif (z = 4) then
            hundreds <= thousands - 400;
            seg_2 <= "0100";
   elsif (z = 5) then
            hundreds <= thousands - 500;
            seg_2 <= "0101";
   elsif (z = 6) then
            hundreds <= thousands - 600;
            seg_2 <= "0110";
   elsif (z = 7) then
            hundreds <= thousands - 700;
            seg_2 <= "0111";
   elsif (z = 8) then
            hundreds <= thousands - 800;
            seg_2 <= "1000";
   elsif (z = 9) then
            hundreds <= thousands - 90;
            seg_2 <= "1001";
   end if;
end process;

do you think this will work as a fix?
 

You might consider using the double dabble algorithm instead of those huge case statements to perform the binary to decimal conversion
 

I'm not sure what you're trying to do, but you're not going to do it with that code.

First, you assign z based on the value of hundreds. Then you assign hundreds based on the value of z. Sounds like an oscillator.

You've got dec in your sensitivity list, and then you don't use dec anywhere. Then, you've got signals hundreds and z, and they're NOT in your sensitivity list.

I think you should draw a state diagram or flow chart to figure out exactly what you're trying to accomplish. I get the sense that you're thinking of this like software (which it's not) rather than hardware.
 

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