Seems to me you would need a counter AND a shift register.
You clock the counter & shift-reg with your sampling clock. Feed the bitstream into the shift register. When the counter hits 8/10/16 whatever - generate a pulse or edge. Then at this edge time, sufficient bits have been shifted in, and you can use this edge to "unload" the shift reg and latch the data into whatever is next in your circuit.
Naturally your shifter length should be >= whatever bit length you have chosen.
Also ... ummm.. you might need to reset your RC integrator with this same pulse/edge.
Hope this helps ?
Counting the number of '1' states over a defined time interval is identical to a first order CIC decimation filter. Usually a higher order filter would be used. You'll find many same topic threads about sigma delta and CIC at edaboard.
That's basically correct, the '1' density is representing the input voltage. In contrast to a simple counter, a first order CIC decimator is working as an accumalator for fractional parts of the input signal, a signal of 0.5 LSB e.g. gives a a output for every second sample. A higher order CIC filters input and quantization noise and achieves a higher resolution.1) To get an 8 bit output we need to count the highs on the itstream for 255 clock periods.
2) It does not matter where in the bitstream we start counting.
Hopefully you do understand it. Your suggested circuit doesn't work as a linear SD-modulator, it should use an integrator and the FF in the feedback loop.You guys don't understand the basics yet want to leap into FPGA across 15 simultaneous channels.
Good luck to YOU
LoL!
That's basically correct, the '1' density is representing the input voltage. In contrast to a simple counter, a first order CIC decimator is working as an accumalator for fractional parts of the input signal, a signal of 0.5 LSB e.g. gives a a output for every second sample. A higher order CIC filters input and quantization noise and achieves a higher resolution.
Usually the decimation filter uses a power of two decimation factor, but that's not necessary.
You'll notice, that SD ADCs have effectively replaced classical slow ADC methods like dual-slope. That's mainly because of their better linearity, which doesn't depend on capacitor loss factors and similar. The oversampling aspect also involves less effort in analog filtering.
Hopefully you do understand it. Your suggested circuit doesn't work as a linear SD-modulator, it should use an integrator and the FF in the feedback loop.
Implementing a low resolution ADC is actually an easy task, and applying it to 15 channels in a FPGA design isn't more difficult than a single channel.
The original question is about a SD modulator used as ADC, in so far we would assume linearity is an obvious requirement. Seriously speaking, I don't believe that the circuit from post #4 will produce accceptable results as shown. I rather guess there's a drawing error involved.
I also think, you shouldn't consider about "OT" after your post #7. It's not the usual style at edaboard to make pointless comments about the technical knowledge of other members. No matter if they seem to be substantiated somehow or pure invention, as presently.
P.S.: A more promising SD variant in my view
wow.
You guys don't understand the basics yet want to leap into FPGA across 15 simultaneous channels.
Good luck to YOU
LoL!
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