viny9694
Newbie level 2
Hi all,
I'm designing a D flip flop cadence virtuoso 180nm Technology. First, I designed the schematic with 1u/500nm for pmos/nmos (I took randomly), then I performed the simulation. But, getting the output in mV instead of V for 1.8V source. Does size matters? I f so how can I calculate for the below schematics?
Thank you.
I'm designing a D flip flop cadence virtuoso 180nm Technology. First, I designed the schematic with 1u/500nm for pmos/nmos (I took randomly), then I performed the simulation. But, getting the output in mV instead of V for 1.8V source. Does size matters? I f so how can I calculate for the below schematics?
Thank you.