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tarkyss said:I can not find variables of some vhdl sub modules in modelsim objects windows
why?
thanks
p1 : process
variable a_var : bit;
begin
wait;
end process p1;
log /top/dut/p1/a_var
log /top/dut/p1/*
Buğra said:Hi
İm begineer in FPGA and VHDL. im trying to make a fir filter,,i did almost, i wanted to simulate but there is some mistakes, i want to correct it , but i didnt find where it is. i wanted to see variables in modelsim,,but i couldnt find how. here a friend explained sth but i didnt understand where will i write them etc... is there anyone who knows it a simple way? thanks...
Added after 22 minutes:
ok guys,, i found the way,,for friends who has the same problems..
*give a name to process
*add process tool to toolbar
*right click to name of process in process tool and display option.
*select in region mode, and it will browse click ok. thats all..