How: Bidirectional port at FPGA

[PigiPigi]

Hi my friends,
I like to implement a bidirectional data bus (port to externl memory) at Xil FPGA that have bidrectional port. How can i do that.

 

[zyphor]

First you 'd better use Mutiplexer to replace Bidirectional port.
Second If you still want to Bidirectional port, pls desribe circuit like this:


--------| PAD
|
_____|\_____________ |---\
|/ | |__/
|
|
_______ /| __|
\|

 

[Ace-X]

ENTITY example IS
PORT( out_en : IN STD_LOGIC;
in_bus : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_bus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bi_bus : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0));
ARCHITECTURE rtl OF example IS
BEGIN
out_bus<=bi_bus;
bi_bus<=in_bus WHEN out_en='0' else (others => 'Z');
END rtl;