how am I supposed to do with ungated flop?

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coshy

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Hi.

When I run the synthesis, I've got a lot of ungated flops.
I think I need to add block level clock gating, but I also need to change my cording to allow for more clock gate being inferenced. But I'm not sure how to improve this.
Can you help me how to improve this problem? Any cording guide or methodologies or some guide.
 

Basically the coding style of gating FF would be:

Code: 
always @ ( posedge clk ) begin
   if ( [B]en[/B] ) out <= in;
   else      out <= 0;  
end
Ussually with an enable signal for the output to be active.


If a Flop was not gated, its Verilog code should be:
Code: 
always @ ( posedge clk ) begin
   out <= in;
end
There are a lot more variants of coding styles can bring you the gated flop.
Looking for gating technique online.
 
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    coshy

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By the looks of it, you don't know what you are talking about. Maybe review some literature on clock gating, coding styles, and power gating.
 

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