how about the effect of a float nwell

[vagary]

floating nwell

in layout. if there is a float nwell, what kind of effect it will arise?

 

[Hughes]

floating n-well

The circuit is subject to latch-up.

 

[vagary]

floating n-well pnp latchup

why? can you explain more?

 

[kwkam]

floating nxwell

parasitics PNP ! Actually, the pmos can't work at all !

 

[bastos4321]

what is n-well floating error?

A float nwell is usualy used to cancel body effect in PMOS diferential parir in amplifiers.

The problem is that this well has a capacitance to substrate that has at least two effects:

1- Injection of substrate noise in the node.
2- PSRR gets degradate due to the lower pole frequency in that node.

I do not understand the anwsers from kwkam and Hughes. Can they please explain.

"parasitics PNP ! Actually, the pmos can't work at all !" ??????

Yes they can, this is normal in analog amplifiers.

"The circuit is subject to latch-up. " ??????????????

No its not.

Regards Bastos

 

[Hughes]

floating n well

If nwell is floating, the current through PMOST may drive forward the P+/NWELL diode, the emmiter of the parasitic vertical pnp bipolor. Thus comes the susceptibility to latchup. Even latchup is not occur, the subthreshold characteristic of the PMOST will be deteriorated, the off-leakage of PMOST will increase.

Hi, bastos4321,
I suppose you are talking about source-connected nwell rather than floating nwell. I never seen an analog amplifier with floating nwell in bulk silicon process. To cancel the body effect of PMOS, the substrate of PMOST(nwell) is connected to its source, but not floating.

 

[joe2moon]

nwell floating

I agree with Hughes !

After reading bastos4321's post, I'm confusing at the definition of "floating" .
(*** Misunderstanding about the meaning of "floating" ***)

So, if N-well is floating, then
1) [P+/NWELL diode may be forward] leakage current (Hughes)
2) [ no substrate contact ] injection of substrate noise (bastos4321)
3) [ 2) may result in this] susceptive to latch-up (Hughes)

 

[rfsystem]

floating nwell latchup

The diffpair application is the most used to connect the NWELL other than VDD. But also in the diffpair transient situation could lead to an ON condition of the P+/NWELL/PSUB pnp. In some circuits the free NWELL conncetion is used for isolation and reduction of the substrate effect on the threshold voltage. I would prefer to use a complex PMOS model including the parastic pnp if free NWELLs containing pmos are used. Through simulation you could detect much easier malfunction.