rf1008
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Hello,all,
Pls. help to advise how about the phoise noise of my PLL. Three loop bandwidth have been tried and attached,5K,10K and 20K,and the actual bandwidth in spectrum analyzer is much wider.
Different bandwidth different phase noise,and even the lock time.
How about the three curves,please kindly advise how to improve more. Of course the lower of in-band and out-band noise the better. and the PLL is from ADI's ADF4360-7, here is it,https://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4360-7/products/product.html
I used signal generator to replace my OSC and found nothing improved,and also the bypass caps of VCO are modified. thanks.
Pls. help to advise how about the phoise noise of my PLL. Three loop bandwidth have been tried and attached,5K,10K and 20K,and the actual bandwidth in spectrum analyzer is much wider.
Different bandwidth different phase noise,and even the lock time.
How about the three curves,please kindly advise how to improve more. Of course the lower of in-band and out-band noise the better. and the PLL is from ADI's ADF4360-7, here is it,https://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4360-7/products/product.html
I used signal generator to replace my OSC and found nothing improved,and also the bypass caps of VCO are modified. thanks.