[SOLVED] Homebrew astable not working correctly but as monostable does.

[d123]

Hi,

Sorry, this thread/question will be hard to understand from the assorted hand-drawn schematics and my usual endless blather, even for me, so not expecting much inclination for anyone to parse the images of sub-circuits and the lengthy descriptions. Anyway, any help appreciated.

Circuit design goal was a 'non-retriggerable, once and once only one-shot with negative-going input signal'. Achieved, except did positive-going input. It reeks of hobbyist territory but is quite flexible as a circuit...

Description by stages:

A re-triggerable monostable:

A re-triggerable monostable with on-delay:

Adding this section makes it a non-retriggerable, once and once only monostable that power cycling resets:

It only needs a POR RCD to auto-trigger at power-up:

... I got 'mission creep' syndrome and out of my admiration for Hans Camenzind and his incredibly versatile and ubiquitous (but we all criticize it...) clever little timer IC, I wanted to get my circuit to at least do astable as well - mark-to-space is set by C1 and C2 selection in my circuit and Q13 is Vout for that (it also works with a push-pull/totempole output stage, not just a PMOS drain output).

Problem: Re-triggerable and non-retriggerable monostable with or without on-delay works great.

Astable version doesn't work - Q8b and Q13 signals end up overlapping as Q13 (C2 presumably doesn't drain as fast as needed) lingers on longer than desired and so Q8b turns back on too soon. The larger the capacitors, the worse it becomes, until it's embarrassing to look at.

I tried making R10 and R23 100 Ohms to drain the timing caps faster but it makes no difference. I made some of the 2k2 sink resistors 330 Ohms to speed up turn off, but it makes no difference. Will try changing R11 and R25 1k in case that helps.

Any suggestions or guesses as to why the astable signals end up overlapping, even if C1 is only 100uF and C2 is 220uF?

Thanks.

 

[KlausST]

Hi,

may I ask why you try to do this with discrete parts?
It´s a lot of effort, many parts...
(I´d never go this way)

I´m sure ther are integrated solutions.

Klaus

 

[d123]

Hi Klaus,

I'm sure there are, and that cost pennies. I know what you mean. To answer your question - I do these circuits because I enjoy these challenges/puzzles, I get to use my brain a bit, it's a healthy pastime, and I learn things along the way about a hobby I very much like. Knowing discrete design and building blocks is useful, I believe. I'm not a proponent of the 'analog design is dead' notion, I very much enjoy analog design.
Having said that, if/when my life goes back to normal, I hope to learn to use some MCUs a nice person gave me, now is not the right situation for extended learning curves of new devices and concepts like coding, sadly.
And, for this circuit, I have a fondness for the 555 (it was the first IC I ever used, amazed me back then, and is probably what got me into electronics as a hobby) but the times I've quickly tried to copy it, it never works, so this has been a rewarding experience and may help with that project/someday goal.

The rain has stopped after several days and the sun came out so I was finally able to do the schematic capture and a non-frustrating simulation this afternoon. The simulation works for the non-retriggerable input but not for the re-triggerable input, and time-step had to be changed from 10G to 1m in order to get results the same as/very similar to reality. 2N2222 POR bit is not part of the circuit, was needed to simulate power cycling...

Okay, later it'll be back to attempting to get the astable option to work, but I'm not expecting much success with that aspect of this circuit.

 

[KlausST]

Hi,

O.K. I understand. But don´t have the time now to go through the whole schematic.
I´ll follow this thread..

Klaus

 

[d123]

Hi again, Klaus,

Don't worry, and thanks.

I think some of us (maybe me, and definitely with this circuit), who do know what a circuit does from designing it ourselves and having battled with the bits that need more effort to make them functional expect others to just easily read the schematic of it and understand it as well as we do - not comprehending that what is by that point a familiar 'language' to oneself, in fact just looks like a load of components connected together and Lord knows what they do or don't do or are supposed to do to someone else and therefore the schematic and questions may as well be written in a language like Martian.
I'm not expecting anyone to even bother looking at it, understand each bit without a helpful guided tour, nor try to troubleshoot the transistor soup it looks like...

Once again, thanks.

 

[d123]

Hi,

... Problem is an elementary issue. Stupid me, seems obvious now. R10 and R23, and R11 and R25 need to be progressively smaller as the timing capacitors get larger. Works okay as astable for low value capacitors but needs e.g. presumably 10 Ohms capacitor drain resistor for even 220uF to avoid slight overlap (I stopped experimenting at 33 Ohms on seeing the overlap decreasing with each smaller resistor used) and it gets worse from there upwards. Oh well.