krippkrupp
Newbie level 5
I'm using Pulpino from github. I've changed the RAM and removed some of the peripherals.
I've passed both RTL and post-synthesis simulations with results as expected.
In the P&R after nano route, when i run
and
both the hold and the setup slack is 0.
However when I run the simulation, some of the cells are reporting error for hold violation. The exact message is..
What could be the reason for a hold violation in post layout simulation even though PnR shows that both hold and setup times are fine?
I'm using on chip variation, in order to be able to do postRoute optimization.
Thank you in advance,
Stoffe
I've passed both RTL and post-synthesis simulations with results as expected.
In the P&R after nano route, when i run
Sass:
report_timing -early
Sass:
report_timing -late
Code:
------------------------------------------------------------
optDesign Final SI Timing Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+
| Setup mode | all | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
| WNS (ns):| 0.000 | 0.000 | 13.178 | 15.022 |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 | 0 |
| All Paths:| 24310 | 24232 | 63 | 15 |
+--------------------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+
| Hold mode | all | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
| WNS (ns):| 0.399 | 0.399 | 0.402 | 0.400 |
| TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 0 | 0 | 0 | 0 |
| All Paths:| 24310 | 24232 | 63 | 15 |
+--------------------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 1 (1) | -0.000 | 17 (17) |
| max_tran | 0 (0) | 0.000 | 20 (447) |
| max_fanout | 0 (0) | 0 | 66 (66) |
| max_length | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 10.868%
Total number of glitch violations: 0
------------------------------------------------------------However when I run the simulation, some of the cells are reporting error for hold violation. The exact message is..
I can also see which register the hold violation is taking place in.
What could be the reason for a hold violation in post layout simulation even though PnR shows that both hold and setup times are fine?
I'm using on chip variation, in order to be able to do postRoute optimization.
Thank you in advance,
Stoffe
Last edited: