Hold violation post-layout simulation

[krippkrupp]

I'm using Pulpino from github. I've changed the RAM and removed some of the peripherals.
I've passed both RTL and post-synthesis simulations with results as expected.
In the P&R after nano route, when i run

report_timing -early

and

report_timing -late

both the hold and the setup slack is 0.

------------------------------------------------------------
     optDesign Final SI Timing Summary                             
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+
|     Setup mode     |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):|  0.000  |  0.000  | 13.178  | 15.022  |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |
|    Violating Paths:|    0    |    0    |    0    |    0    |
|          All Paths:|  24310  |  24232  |   63    |   15    |
+--------------------+---------+---------+---------+---------+
+--------------------+---------+---------+---------+---------+
|     Hold mode      |   all   | reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|           WNS (ns):|  0.399  |  0.399  |  0.402  |  0.400  |
|           TNS (ns):|  0.000  |  0.000  |  0.000  |  0.000  |
|    Violating Paths:|    0    |    0    |    0    |    0    |
|          All Paths:|  24310  |  24232  |   63    |   15    |
+--------------------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
|                |              Real             |       Total      |
|    DRVs        +------------------+------------+------------------|
|                |  Nr nets(terms)  | Worst Vio  |  Nr nets(terms)  |
+----------------+------------------+------------+------------------+
|   max_cap      |      1 (1)       |   -0.000   |     17 (17)      |
|   max_tran     |      0 (0)       |   0.000    |     20 (447)     |
|   max_fanout   |      0 (0)       |     0      |     66 (66)      |
|   max_length   |      0 (0)       |     0      |      0 (0)       |
+----------------+------------------+------------+------------------+
Density: 10.868%
Total number of glitch violations: 0
------------------------------------------------------------

However when I run the simulation, some of the cells are reporting error for hold violation. The exact message is..

$hold( posedge CP: TIME ps, negedge D &&& dSN: TIME ps, 10 ps)

I can also see which register the hold violation is taking place in.

What could be the reason for a hold violation in post layout simulation even though PnR shows that both hold and setup times are fine?


I'm using on chip variation, in order to be able to do postRoute optimization.

Thank you in advance,
Stoffe

 

[krippkrupp]

Looking at the wave where the first hold time violation that occurs, I can see that the data D arrives at the same time as the clock CP in data_int_reg[8]. How can this be since the WNS hold in the PNR result is 0.4ns?

I have tried simulating with and without the SDF-file, and the result is the same.
In encounter, I've tried with ideal clock, without ideal clock with active view SS and FF. No changes in the simulation result.

As of now, I'm trying to solve this completely blindfolded, looking for any warning that could be the cause of the issue.

When I load the SDF-file, I get the warning
Warning: (vsim-SDF-3924) .../delayfile.sdf: Out of 1022840 SDF statements, 1022840 hade null values.
I assume this is because the typ values are missing? For example, the values looks like (0.001::0.002). Are the typ values needed and what could be the reason they are missing? I looked through the commands
If I try to change to 'min' or 'max' instead of 'typ' when reading the SDF-file in questasim, I get the following error:
Warning: (vsim-SDF-3262) .../delayfile.sdf: Failed to matching specify timing constraint.

I'm not sure if this issue with the SDF-file is a red herring or if I should continue to look in that direction. However, since running PL sim without the SDF still causes the issues - which it shouldn't if I'm not mistaken

 

[ThisIsNotSam]

first thing I would check is how delay is calculated in your simulation. the std cell verilog models are always tricky, sometimes a mix of real timed paths with unit delays. sometimes there are pragmas/directives for you to do enable or disable

since your simulation with SDF and without SDF gives the same answer, most likely the problem lies in there

 

[krippkrupp]

Thank you for your reply. I solved the issue last night. Turns out I had forgot to specify that there were multiple clock domains - stupid mistake.

 

[Qwerty112233]

To be sure, do you mean launch and capture were diff clocks? And you missed that constraint in your pnr?

 

[krippkrupp]

To be sure, do you mean launch and capture were diff clocks? And you missed that constraint in your pnr?

Besides the main clock, I had a couple of external clock sources to two peripherals, SPI and JTAG. I didn't define those as clock sources during synthesis hence neither were affected by the clock tree and thus not fulfilling the needed hold and setup slack