Hold Violation Fixing

[pshah32]

Hi,
I have hold violations in few corners. To fix those I have few queries:
1. How to decide that when to add buffer/ resize some cell ?
2. I have lots of buffers in lib which I can use to fix the violations.
I have a table for all buffers mentioning drive strength and delays for each one.
My question is shall I only consider delay as my criteria and blindly fix the violation by inserting a buffer ?
3. How can I know which drive strength buffer is suitable in the violating path?

Suppose we have 1000ps violation then I can use x2,x4,x6 any buffer to fix. Setup is not a problem as I have almost 3000ps of setup margin avail.
How to select a right buffer ?

Please help me to understand the criteria. Also it would be helpful if you can explain with PT commands.


Thanks,
Puneet

 

[dhaval4987]

I am interested in knowing this answer.

 

[trav1s]

You will have to look at the load that the buffer is driving, meaning the net and the input pins of connected instances. Each buffer should have a specified maximum fanout and maximum capacitance that it can drive. Consult your technology library for these values. You then have to find the number of loads, and calculate the capacitance of the affected net.

First, you should eliminate any buffers that do not satisfy the number of loads or capacitance on the particular net.

Next, select a buffer (or buffers) based on your design goals. For instance, if your goal is low-power, you want to avoid the big drivers unless absolutely necessary. Finally, make sure the buffer (or combination of buffers) total delay is between 1ns and 3ns, otherwise you will still have timing violations.

If you have multiple sizes of the instance driving the net with the timing violation, you may not need to use a buffer at all. Look at the delays, max fanouts, max capacitances of these instances, and eliminate those that do not satisfy the requirement. But how do you choose whether to use a buffer or just resize the instance? Again, it goes back to your design goals. Do you want low gate-count? Low power? Small area? You should choose the implementation based on what you are optimizing for.

 

[pshah32]

Thanks for the reply.

But I have one query:
We have design linked and library is loaded in primetime. I want to know if there is any command to look at the delays, max fanouts, max capacitances of these instances in PrimeTime.
This would be very handy and useful.

I guess we can see these properties in lib file but it is not handy because these files are too big to open and also very difficult to read, as it has details about all modes and corners.

It would be good if we use can see this information in PT because we already have particular PT session loaded and we just want to see properties of buffer with respect to current session rather than struggling with lib files.

Regards,
Puneet

 

[trav1s]

Also, please specify what "PT" is.

---------- Post added at 17:32 ---------- Previous post was at 17:28 ----------

Ah, I am unfamiliar with PrimeTime, sorry. However, I know that in Cadence Encounter, the tool can automatically fix timing violations for you, and optimizes the choice based on your design constraints. I am sure your set of tools does something similar. I don't want to be the jerk that says "go read the manual" ... but I really don't know the answer to that question.

 

[pshah32]

Prime Time Tool.

Also, how to decide whether to use inverter pair or 1 buffer ?

---------- Post added at 09:36 ---------- Previous post was at 09:33 ----------

I spent lot of time finding solution for this in command reference but didnot succeed.

 

[trav1s]

Library designers usually implement a buffer by using inverter pairs anyway. Usually they are squeezed tightly together though, so you will probably get a small area benefit from using 1 buffer over 2 inverters of the same power, drive strength and speed.

 

[rca]

To fix remaining hold time after the hold time step (in Encounter):
1-the first way is to increase the hold time margin during the post-route timing optimisation phase. this marging will be only apply on remaining path , and not for all path, as it could be done during the hold time step.
2- First easy think in Encounter is to upgrade the drive strengh of the buffer.
3- If Primetime finds some hold time violation:
a- add buffer in Primetime based on the report, and re-checked the result.
b- export a script which include the buffer to be added on the netlist, Primetime could not modify the netlist, the script is made for Design Compiler, command write_change
c- in design compiler modify the netlist
d- Do an ECO mode to add this new buffer in Encounter.. place & route and return to Primetime to check the hold.


I have used all of them, I prefer the first one.
good luck.

 

[samarah]

Thanks for the reply.

But I have one query:
We have design linked and library is loaded in primetime. I want to know if there is any command to look at the delays, max fanouts, max capacitances of these instances in PrimeTime.
Puneet

In DC, you type the following to get the max cap at the output pin
get_attribute $stdCellsLib0/$Cell/$outPin max_capacitance

and to get the input cap at some input pins, type
get_attribute $stdCellsLib0/$Cell/$inPin capacitance

properely, it's the same in PT

 

[cop02ia]

To decide whether it would be better using inverter pair or buffer depends on the design & timing violation.
An inverter pair would in general introduce more delay since it uses 2 cells instead of 1.
Having said that, if the clock net is really, really long, the inverter pair might actually reduce the original delay, depending where it is placed (using 1 buffer would also reduce the delay of the long net but maybe not as much as the inverter pair).
You can estimate with some back of the envelope calculations (rem. delay is proportional to net length squared).

If the tool cannot meet timing violations slightly, ECO alone may be sufficient - I usually start with changing the cell sizing first before consider inserting additional cells.
My strategy is to let the tools concentrate on fixing hold violations as any changes on the clock tree effects a lot of paths - if manual fixing is needed, I'd rather have a design where setup violations to be manually fixed rather than hold violations.
Perhaps other people have a better approach.

Best regards,
I-FAB