Hold violation fixing before CTS

[kumar_eee]

What is the reason behind fixing the Hold violations after the CTS?

 

[navateja]

Before CTS, the clock is ideal. It means that the values of the skew and slew are not accurate. They are just the approximate values. But after CTS, the clock is propagated. It means that the skew is balanced. Also, the transition times of the clock(s) along with the input and output rise and fall times can be known. The balancing of the clock skew across the network is achieved by inserting buffers (not ordinary buffers, but special clock buffers) in the clock path.
Also it is known that the hold violation is more dangerous than setup violation. This is because setup violation can be fixed by decreasing the frequency of operation of the circuit. But this is not the case with hold. Even if the hold fix is done before the CTS stage, the additional buffers in the clock path add up (or in some cases reduce) certain amount of delay. Hence, it is always recommended to fix the hold violations after the CTS stage.

Hope this helps.

 

[ebuddy]

Don't you also need to fix setup violation after CTS? The timing information from layout is valid only after CTS.

 

[navateja]

We also fix setup violations after CTS. All that I'm telling is setup is related to the delays in the data path and the hold is related to the delays in the clock path. So, setup can be fixed in the pre-CTS stages (even when the exact clock delays including the buffers delay is not exactly known). But for the hold fix, the exact delay of the clock path is needed. Hence hold violation needs to be fixed post-CTS.

 

[lostinxlation]

Both of setup and hold fixes requires the exact path delay as well as the exact clock insertion delay, so in theory, both should be fixed after CTS. The only reason we fix the setup time before CTS is that it's a bit too late to do so after CTS. After CTS, all the cells are placed and you don't have much flexibility in fixing the setup time. On the other hand, fixing hold is just adding the buffers and is easily done even after placement.
If the tool becomes sophisticated enough to handle the setup time fix even after placement, we don't need to fix the setup before CTS. Basically, it's mainly due to the tool limitation.

 

[jeevan.life]

Both of setup and hold fixes requires the exact path delay as well as the exact clock insertion delay, so in theory, both should be fixed after CTS. The only reason we fix the setup time before CTS is that it's a bit too late to do so after CTS. After CTS, all the cells are placed and you don't have much flexibility in fixing the setup time. On the other hand, fixing hold is just adding the buffers and is easily done even after placement.
If the tool becomes sophisticated enough to handle the setup time fix even after placement, we don't need to fix the setup before CTS. Basically, it's mainly due to the tool limitation.

And also we can play around with clock frequency to fix setup...but hold is not related to frequency..So !!!

 

[SSTA]

Hi Guys,

I have a question and will really appreciate your answers.
Let's assume that we have 1ns hold violation BEFORE CTS. And assume that skew is 0.
What can be the reason???

Thanks!

 

[ebuddy]

The possible reasons I can think of: 1. The input delay is not set properly; 2. The library you are using has a large hold time requirement.

Hi Guys,

I have a question and will really appreciate your answers.
Let's assume that we have 1ns hold violation BEFORE CTS. And assume that skew is 0.
What can be the reason???

Thanks!

 

[SSTA]

Thanks ebuddy!
No strict answer on this question, right?
So the first is related to the constraints, but here another question, in that case why design compiler was not able to fix it? Do you mean that input delay constraint is unreasonably tight and even the tool is not able to fix with ideal clocks? The second one is also a good point, but may it cause such a huge violation?Not sure.
I never met such situation in my designs, this is something what I think the last days .
Just a point, could this be due to not enough cells in library for creating different logic..? Or something else.

 

[fpgafresh]

Basically both the setup and hold violation analysis is a pessimistic analysis i.e. we want to find the worst failing paths. For this reason when we are analyzing setup time we want to make are clock as fast as possible and data as slow as possible ( we use WC corner for setup analysis). From the point of view of the clock network, the clock delays are minimum before CTS when the clocks are considered ideal and propagation delay of clock network is zero. Thus setup can be analysed for the worst failing path before CTS.

When we are analyzing hold time we want to make clock as slow as we can and data as fast as we can ( BC corner for hold analysis). Again from the point of view of the clock network, the clock delays are maximum after CTS when the clocks are propagated and buffer cells are added in the clock network to balance skew. This hold can be analysed for the worst failing path after CTS

 

[pavanks]

You need to fix hold always after CTS coz, before CTS u dont have ur real clock tree propagated from the clock source to the clock pin of ur flip flops.
So the clock path is ideal before CTS.
As we know that hold is anlaysed on the same clock edge. So we need to know the exact same clock edges at the two flip flops communicating considering if there is a skew between them. So we get the real clock edges after clock routing.
Hold violated means that u lost the functionality of ur design.

 

[Raghu Chowdary]

i didn't understand ,,could you explain me in detail about why we dont do hold analysis before CTS?