Hold values

LVT and SVT do not have hold values. Cells can have hold values, paths can have hold timing.

Assuming you mean a path that has LVT cells in it... it means it is faster and therefore creates potential hold violations more easily than SVT would.

ThisIsNotSam said:

LVT and SVT do not have hold values. Cells can have hold values, paths can have hold timing.

Assuming you mean a path that has LVT cells in it... it means it is faster and therefore creates potential hold violations more easily than SVT would.

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I meant to ask, if I have 1 cell in lvt flavour and the same cell in svt flavour. How would their hold values change for the same data and clock slew values. From my observation for the same data and clock slew, hold is in magnitude greater for lvt than svt but only in magnitude

Hold-time required is also a function of flip-flop
design. We used to prefer to design for zero hold
time. But nonzero signal hold time incoming is a
normal outcome of 'flop delay and any subsequent
logic before the next register.

I'd consider it a poor cell library design, if 'flops
required more hold time than their natural delay
(if chained with a uniform clock-front, and no
interstage logic, still no worries would be my goal).

randomname56 said:

I meant to ask, if I have 1 cell in lvt flavour and the same cell in svt flavour. How would their hold values change for the same data and clock slew values. From my observation for the same data and clock slew, hold is in magnitude greater for lvt than svt but only in magnitude

Click to expand...

Your terminology still confuses me. Combinational cells don't have hold values, only FF have hold constraints. Are you talking about FFs?

ThisIsNotSam said:

Your terminology still confuses me. Combinational cells don't have hold values, only FF have hold constraints. Are you talking about FFs?

Click to expand...

Yes yes

In principle, an LVT FF can have a different architecture than an SVT FF. In most cases, the layout is identical and only the doping is different, making the cell faster. Faster = bad for hold. This is the simple explanation. To understand why, you would have to do SPICE simulation of the FF layout/schematic and then you will get where the difference comes from. Most likely the SVT FF registers a '1' at 0.5V while the LVT FF registers it at 0.4V. (arbitrary numbers but give you an idea)