Hold time in synchronous design

In Synchronous digital design, signals are sampled and changed at the clock edge. If a signal change at the clock edge, doesn't the register receiving this signal violate the hold time because the signal changes shortly after the clock edge?

Is c to q delay + propagation generally greater than the hold time or do we have to design this way?

parkpika said:

In Synchronous digital design, signals are sampled and changed at the clock edge. If a signal change at the clock edge, doesn't the register receiving this signal violate the hold time because the signal changes shortly after the clock edge?Is c to q delay + propagation generally greater than the hold time or do we have to design this way?

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If there is one commandment for reliable, problem-free design, it is synchronous design.I think you are understanding it the wrong way.At the rising edge of clock,after i/p is kept constant for a time equal to setup time before edge & hold time after clock edge,then only i/p changes.There is no hold time violation over there

I assume c is i/p & q is o/p of register,them propagation delay >= thold.

No I mean, imagine two shift registers. In a synchronous design, The first register's output changes at the clock edge. This output is the D input to the 2nd register. Wouldn't this D input violate the hold time of the 2nd register because it changes shortly after the clock edge?

Is c to q delay + propagation generally greater than the hold time or do we have to design this way?

I'm just confused because in simulation, the signals changes exactly at the clock edge.

parkpika said:

No I mean, imagine two shift registers. In a synchronous design, The first register's output changes at the clock edge. This output is the D input to the 2nd register. Wouldn't this D input violate the hold time of the 2nd register because it changes shortly after the clock edge?

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See the attachment.The o/p of the first register becomes stable after hold time.This o/p is i/p of second shift register.So,there is no question of hold-time.
There may be a problem of set-up time if your propagation delay is high.

parkpika said:

Is c to q delay + propagation generally greater than the hold time or do we have to design this way?

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It is greater than hold time.How can design propagation delay ???

parkpika said:

I'm just confused because in simulation, the signals changes exactly at the clock edge.

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Can you show your simulation.Try to adjust clock period so that there is no set-up/hold time violations.

Ah, so you are saying the output of the register changes after its hold time (i.e c-q delay > hold time).

Where is the attachment?

The attachments got deleted,i think.