parasuraman
Newbie level 1
hi friendz...
i am newer to verilog desgin.while simulation of my verilog code in cadence it find the infinte loop design. so that i couldn't get the simulation result .but in xilinx i got the result for that design..... can you help me for the same...
i am newer to verilog desgin.while simulation of my verilog code in cadence it find the infinte loop design. so that i couldn't get the simulation result .but in xilinx i got the result for that design..... can you help me for the same...