Highest Operating Rate for 82C55 and DIO 96..

[dhruvish]

Hello Guys,

I have gone through data sheets of both, couldn't find which is the max data rate at which the 82C55 and DIO 96 can be operated. I need more materials on these chips. I am sure somebody can help me with this.

Thanks,
D

 

[papyaki]

Hi,

For 82C55A, I think you must take in account the duration of a single read or single write plus the time time between two consecutive read or write.

read pulse width tRR= 150ns
time between two reads/writes tRV= 300ns.

The total for 82C55A is 450ns. If you add 50ns marging, this give one acces every 500ns, or 2MHz for aquisition frequency.

For 82C55A-5, tRR = 250ns and tRV=300ns. The total is 550ns. By adding 50ns marging, the total is 600ns or 1.6MHz.

 

[dhruvish]

Hi,

I have some more doubts over the DIO-96 from NI. They say it uses four 8255 chips. But I dont see as many pins, I only see 24 I/O pins for each block of 8255 but what heppened to other control pins? Isn't there any control bits in NI DIO 96?

Please make it clear
D

 

[papyaki]

Hi,

I had a look at NI site. DIO 96 seems to be a bord using four 8255. You only have access to the IO connector which is wirred to the IO pins of the four 8255. Control pins of the four 8255 are driven by a logic interface between the host PC (ISA or PCI bus) where the DIO 96 is plugged into.