High voltage can't into sat. region when Id is small.

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mpig09

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Hi all:

I am design a current mirror, and this circuit is used in a LDO,
so the quiescent current needs to small.

But I found the W/L of the high voltage MOS(NM5 and NM7) is big (20u/1.6u), so the NM5 and NM7 can't into the sat. region when the current is small (< 5uA).

Could you give me some suggestion?
(other structure or design note for the attached file and ...)

Thanks.
mpig
 

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  • Current_Mirror.jpg
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Hi, mpig09
I didn't get why are you cascading two MOSFETs as long as first section of your current mirror indicates that you are going to design an effective MOS by simply connecting both gate terminals together and source to drain? Is it necessary for your architecture, if not then try for simple current mirror you can get your specified current.
 

mpig09 said:
... the NM5 and NM7 can't into the sat. region when the current is small (< 5uA).
Click to expand...

vds ≫ vdsat (by a factor of ≈10) for both NM5 & NM7, so they're well in saturation, aren't they?
 

Hi rishabh_31ec:

The current mirror bias a folding cascode OPA, and I want to get a large swing (the min. vout is 0.5V) and good current mirror performance at PVT variation.


*****************************************************************
Hi erikl :

Because the vgs < vth, so I think the MOS is not in the sat. region.
For High Voltage MOS, the min. W/L is fixed, so I can't reduce the W to get big
Vgs.

Thanks for your reply.

mpig
 

Hi to all,

if Vgs < Vth, why does current mirror working properly (currents are equals)?
 

mpig09 said:
Hi erikl :
Because the vgs < vth, so I think the MOS is not in the sat. region.
Click to expand...

That doesn't matter. Due to their large W/L ratio, these transistors work in subthreshold mode, i.e. in moderate or even weak inversion mode. The saturation voltage in this region of operation is very low, in the order of 4*thermalVoltage, i.e @ about 100mV (@25°C). So with vds > 500mV they work well in saturation region.

You can verify this, if you simulate and plot the output characteristic of these transistors (Ids vs. Vds, with Vgs as parameter).

mpig09 said:
For High Voltage MOS, the min. W/L is fixed, so I can't reduce the W to get big Vgs.
Click to expand...
Yes, I know. Doesn't matter.
 
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    sarge

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Hi sarge and erikl :

Thanks for your reply.

I simulate two condition:

<1> MOS_I_vgs2.jpg is sweep vgs to get Ids.
The simulation result shows: mos vth is 0.71V.
When vgs = 0.7V, the Ids is > 1uA.

<2> MOS_I_vgs.jpg is add a dc current, and the vgs is 0.5V (vgs < vth)
the ids of MOS is correct.

Because I didn't have any Design experience in HV MOS,
so the simulation result is confused me.

Does the vgs < vth condition of HV MOS be allowed in the circuit design?

Thanks.
mpig
 

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  • MOS_I_vgs2.jpg
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  • MOS_I_vgs.jpg
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mpig09 said:
Does the vgs < vth condition of HV MOS be allowed in the circuit design?
Click to expand...

Of course! Subthreshold (or weak inversion) operation is standard for low power circuits!

See here the begin of the saturation region VDS,sat (transition from triode to saturation region) for a 64/4 0.18µm nMOS transistor. VDS,sat <≈ 100mV in subthreshold mode of operation:

 
Last edited:

Hi erikl :

In Subthreshold region, the circuit has big PVT variation, is it right?

So if my circuit(current mirror and OPA) needs operate more accuracy, I need to let MOS in sat. region !?

Thanks.
mpig
 

mpig09 said:
In Subthreshold region, the circuit has big PVT variation, is it right?
So if my circuit(current mirror and OPA) needs operate more accuracy, I need to let MOS in sat. region !?
Click to expand...

Not necessarily. I wouldn't think so. What makes you think so?
 

Hi erikl:

1. The ro will have a big variation by PVT especially in the current mirror
circuit and OPA.
2. vth mismatch will effect MOS current.

I will re-study MOS performance that in Subthreshold region.

If you have any idea, please let me know.

Thanks.
mpig
 

mpig09 said:
1. The ro will have a big variation by PVT especially in the current mirror circuit and OPA.
Click to expand...
And why should this PVT variation be larger in subthreshold than in strong inversion mode?

mpig09 said:
2. vth mismatch will effect MOS current.
Click to expand...
This is true for comparable device sizes. However in subthreshold operation this is compensated by using larger area devices.
 

Hi erikl :

1. The ro will have a big variation by PVT especially in the current mirror circuit and OPA.
==> I think the mos operation point will effect by PVT to cause a big ro
variation. (but I didn't find any doc to discuss it in google)
ex:a. slow corner and low temp., the vth is big so mos operate at
Subthreshold region.
b. fast corner and high temp., the the vth is small, may the mos
operate at sat region.
If mos operate between Subthreshold and sat. region, the ro will
has a big variation.

If I have any mistaje, please correct me.

thanks.
mpig
 

vth variation is irrelevant, because for a current mirror you don't supply Vgs, but a constant current. That's why Vgs (VBN1) adjusts itself automatically.
 

Hi erikl :

Thanks, I understand the concept.
In Subthreshold region, only mirror mismatch will be effect, right?
(Because the model doesn't have monto carlo parameter, so I can't verify it.)

Because the current mirror biases a OPA, so the MOS of OPA in Subthreshold is
not allow, right?

Thanks.
mpig
 

Re: Subthreshold mode

mpig09 said:
In Subthreshold region, only mirror mismatch will be effect, right?
(Because the model doesn't have monto carlo parameter, so I can't verify it.)
Click to expand...
You could estimate the mirror mismatch, if you can get the local Aβ (current mismatch) parameter of your foundry's process.

mpig09 said:
Because the current mirror biases a OPA, so the MOS of OPA in Subthreshold is not allow, right?
Click to expand...
Why shouldn't it be allowed? I don't think you understand subthreshold operation. Check this thread, e.g.
 
Last edited:

Hi erikl :

I view the thread, and review all the reply that in my question,
but I am not smart, I still don't know the advantages and disadvantages
between sat and subthreshold when I design a OPA?

Do you or anyone have free time to share ?

Thanks.
mpig
 

mpig09 said:
... advantages and disadvantages between sat and subthreshold ...
Click to expand...
Again: these are two different animals. You can't tell advantages and disadvantages between them.

mpig09 said:
Do you ... have free time to share ?
Click to expand...

Sorry, no. This is a forum to answer specific questions, not an education institution. This is taught by high schools and universities, or you can learn from textbooks.

For subthreshold mode operation I'd suggest to study David M. Binkley's book "Tradeoffs and Optimization in Analog CMOS Design".
 

Hi erikl and all:

Thanks for your reply.
It is helpful me.

I will study David M. Binkley's book "Tradeoffs and Optimization in Analog CMOS Design".

I hope my Knowledge is increasingly progressive.

Thanks again.
mpig
 

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