High voltage buck converter gate driver glitching IRS21867

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Anton Dahr

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Hi,

I have been unable to solve this problem for a while so I'm asking for advice.
I'm working on a 330V step-down regulator with a 100kHz frequency.

It is hard switching. Connected to the output is an inductor-capacitor low-pass filter.
The gate drive bus is 12V.



The high side gate voltage drops when current starts to increase at around 1A and at higher current it randomly turns off prematurely. The red is the high side gate and the blue is the low side. (Don't mind the noise on the blue trace, it is because the ground clamp is on the red probe.)


You can see the voltage drop on the right pulse and below it turns off prematurely:



The drop happens about 100ns after turn-on so I have been suspecting that the gate driver input signal drops since the propagation delay is about the same time, but adding 10pF from the input pin to GND did not help. I also tried replacing R66 with 100Ohm and with 330pF to GND also with no improvement. (The resistors R66, R67 has saved the life of the MCU several times.) Replacing the gate resistors with 10Ohms give a slight improvement but I can't increase them more.

Running from a PSU at 60V instead of from mains there is no glitching even at several amps. The HV_BUS has 470uF and the gate drive bus 220uF and as you can see some ceramic caps close to the driver IC.

Thanks for your interest and any help!
 

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If higher voltage makes the problem, maybe capacitive effects in mosfets affect drive more.. I haven't looked at the datasheet (i hope you have) of the driver ic but nothing unusual sticks to my eye on the circuit as far as shown..maybe layout issue..it's already almost on lw broadcast band..? ..not to say that i know anything about anything..
--- Updated ---

..meaning eg. some common mode interference messes up the pwm controller or something other weird stuff going on..you don't accidentally have high dv/dt on heatsink..? (eg. open grounding, etc..)..
 

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You are learning that higher Vin and too aggressive gate drive = more and more RFI as the Vin climbs and the required output power climbs - this is a classic newbie issue and the reason why a 330V buck converter would be done at 50kHz, with appropriate gate drive and snubbing to limit dv/dt and di/dt in the power circuit - so that it has some hope of passing EMC or even just not interfering with the local control & GD chips.

That said - try soldering a 1uF MLCC 50V directly at the high side gate drive power pins, try also 4u7 on top of this ( also MLCC ) and then another 4u7.

Similarly for pin one - adding caps to Vcc does no harm and may - in all likelihood solve your immediate issues ( until you get to higher HVDC & power anyhow )

Also - change your gate drive R's to 22E for on, with 5E and a series back diode ( 40V 1A schottky ) for turn off ( these are essentially in // with the 5E ) - this will limit the very large amount of RFI you are making at fet turn on.

Reduce the sw freq until the inductor ripple current is as much as the L will handle ( heat wise ) - turning on at low currents is beneficial, turning off higher currents is pretty easy for the mosfets.

Good luck - you'll need plenty - especially if the physical layout is not compact with small current loops.
 

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Hi,

Measure HS Vgs as gate voltage of the HS MOSFET with respect to the source of the HS MOSFET and post back the waveform.
 

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It can be very tricky looking at the high side gate drive without causing more radiation ( RF noise ) due to the leads attached to the switching node.

There is a great article on better ways I saw on linkedin:

The niggles of viewing high side gate drive !

We encounter a lot of budding power electronics engineers trying to look at high side gate drive with varying levels of success. Here is one way - that is reasonably low cost - to look at your high side gate drive with some confidence: Assuming your gate drive is low Z - which it should be: This sug
www.linkedin.com
--- Updated ---

Also - in higher power bucks we normally have variable turn on delay for the lower switch - as when you turn the top switch off the voltage naturally falls, turning the lower fet on AFTER this fall produces A LOT less RFI . . . !
 
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What is your vout and power out?
Anyway, you could do well to do a cascaded buck, and just damp the switch on(s) till the noise problems go.
Cascaded buck can just use a single controller to regulate the final vout.

The method of post #5 looks good to look at the hi side drive....but i wonder if this is also slightly loading the gate drive and so damping away any ringing which would otherwise be seen? Though i guess you just use a higher Inductance GDT till it doesnt load it down so much?
 
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To me the question is just how the LSS source and the driver COM and the signal sources controlling the driver all see the simple pretty little ground wire shown on the schematic.

You say hard switching and rolls on with current, have a look at COM pin referred input pin waveforms for noise margin violations that could make output glitch or invoke some cross conduction protect logic to the same outcome.
 

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Having had a further read of your problem, first try damping the gate switch on....and making the current sense filter heavy enough...it sounds like turn on noise.
Switching fets on too fast is a common problem leading to all kinds of malaise.
 

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It appears Anton has left the building . . .

without commenting - or a thank you . . . (?)
 
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Hi,

Thanks for your help although I haven't solved the problem. I tried increasing the bus clamp capacitors but it had no effect. I'm still thinking it is a false trigger. I didn't mention that I only drive the gate driver logic inputs with 3.3V and while the driver IC claims to be logic compatible that is very close to the max trigger level of 2.5V. It has worked well in some prototypes so there is some randomness to it, therefore I didn't catch this earlier.

I have tried to create a level shifter to increase the 3.3V signals to 12V but I have no components at home except for 5.5V OP-amp lm358L and BJT BC846. The BC846 was very slow at turning off so I couldn't test at high voltage. So before I buy other components I wanted to simulate, but the results I get are weird. Anyone know what is going on? The spice model is for PMST6429 and says that the pins are the correct order. Spice model I tried BC846 too with same result. Another one that worked better but super slow was BC547.



How do you recommend creating a level shifter that has as little delay as possible? If it's inverting I need to make two, otherwise the dead-times can't be controlled but it might be best to do both channels anyway.
 

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Reduce R66, 67 to 220 ohm, and put 33pF to local gnd on the input pins - as short a connection as possible

given the converter " works " @ 60VDC in - the issue is RFI, so turning the fets on slower will help - have you tried this ?

RFI may easily get into what ever electronics you are using to generate the originating GD signals - not shown by OP.
--- Updated ---

. . . some suitable snubbers across the fets not a dumb idea either.
 

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After much experimenting with Kicad simulator I tried LTSpice and got better results. It seems like some models don't work in Kicad but even for those that worked I got slightly different results than with LTSpice. One thing to know is that the pin order is fixed for transistors in spice so it does not conform to datasheets.

I have seen recommendations for level shifters using BJTs but I can't get it to work well in the simulator. There is always a big turn-off delay. A fast mosfet works much better so I will probably buy some. Unless someone thinks I should go with an OP-amp or some logic buffer or something else?
 

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You can buy gate drivers which will take in a 0-3v3 signal and give you your requred gate drive.....whether also elvel shifted or not.
Do you mean like a bootstrap driver?
 

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If the extant GD IC is specified for 3v3 input - then it should work at that - possibly some small filtering needed

messing about with LT spice is unlikely to solve a noise issue.

Cupoftea suggests noise getting into current sense - if you have such - we can't see complete control ckt - but this is a very common newbie issue - noise in the current sense terminating pulses soon after turn on, as no RC filter to the CS pin
 

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Yes, and also, is the layout good, or you are doing this on proto board?
Those bootstrap ccts are highly layout sensitive.
If its a sync buck, then start off without the synch fet, get it working like that, then put in the synch fet.
As EasyPeasy also suggests, i think we need the whole schem.
I will send you a layout doc if you want?
 

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Thanks for your efforts!

I implemented a level shifter on the logic inputs and that made the problem better. It removed the dip but there were still the occasional unintended turn-off, though at higher current than before. I then increased the gate drive to 20Ohms on the high side and the problem went away completely. I will add the anti-parallel diode when I have some to maybe get down the switching losses. Below some pictures for your entertainment!


I didn't update the node names after switching to a Fet, sorry. The gate drive input is connected between R1 and C1.

 

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very good of you to post pictures - you can now go back to the 3v3 drive and see if the slower turn on has removed the need for the level shifter.
 

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