High Voltage 200V high frequency 1MHz pulse generator

Dear Member,
I am working on a research project that involves making a pulse generator
that generates square wave with peak to peak amplitude of 400V (+/- 200 V) at a frequency
of 1 MHz for driving capacitve loads of 50 pF. The design is possible as there are RF plasma generator
working in 2-3KW range with frequency of 13.56 MHz and I have disassembled one such RF generator.
I have come up with a design based on a datasheet/reference design by Microsemi DRF1400 (attached)
I have built it but it isn't working as expected!! And I am trying to figure out the problem hence
I am looking for inputs from members.

The design involves using a variac/auto transformer and a 1:1:1 turn ration isolation transformer.
The output of the secondary side of the transformer is rectified and followed by
bank of high voltage capacitor bank in order to generate the +200V and -200V
output(amplitude can be controlled by the varic connected to the primary side).
This part all working fine. Every thing working as expected!!

The second stage is made of of half bridge.
The high voltage is sent to a half bridge configuration made up of two N-channel
RF power MOSFETs DE150/DE275 from IXYS semiconductor. I don't think there are
equivalent P-channel devices hence the the bridge has to be made of N-channel MOSFETs.
Since both the high and the low side of the bridge are made up of a N-channel MOSFETs
one has to use separate isolated power supplies for generating the gate pulses as the source
of one MOSFET is not at the same potential as the source of the other(separated by potential difference of 400V)
and any gate control voltage is referenced with respect to source!! Also driving MOSFTEs at this high frequency
requires gate drivers as one has to quickly charge and discharge the gate capacitance
to turn on/off the MOSFETs. Interestingly DE150/275 has switching times of 5ns which is
very useful for high speed switching. As far as gate driving is concerned IXYS as single chip
solution IXRFD630 gate drivers which are matched for such application and are capable of
charging gates with surge currents up to 30 Amps!




The third critical aspect of the design is PCB layout as the tracks have to have minimum inductance
and one needs a lot of ground plane with generously placed decoupling capacitors(including tantalum capacitors)
for meeting the surge currents requirements. IXYS as a nice application note as an example for trying out
such designs. I have attached the application note for reference.

The gate control pulses are sent to the MOSFET drivers using Optical fiber cables (using Toshiba TOSLINK cables)
This gives a very high noise immunity to the gate drivers and ensure the pulses are not affected by electrical noise
as these CMOS gate driver chips are susceptible to electrical noise.
Also to ensure both the high and low side transistors are never switched on simultaneously I included another circuit
which ensure the two transistors can't be switched simultaneously. This circuit sends control signal to a Avago HCPL2201
very high speed optocoupler that can work up to 5 MHz.









The problem I am facing is as follows.
1) I can see the MOSFET gate driver generate very clean pulses when the MOSFETs are not connected to
the high voltage source. When connecting the high voltage source (+/-200V tried up to 50V initially)
the gate driver wave form get distorted.



the second image shows the waveform getting distorted.



2) With the lower section of the bridge disconnected and no external load connected but only oscilloscope probe connected to the circuit, the upper
section of the bridge, the seems to be behaving strangely. The MOSFET switches on (pull-up) easily but when the pulse signals transition to low
state the output keeps lingering close to Vcc this happens even at low frequency say 100 KHz, The actual switching off can only be seen for very
low frequency signal say 100 Hz other wise for any frequency higher than that the output stays at Vcc.
My assumption was because when the MOSFET is turned on the charge carriers are pulled to create the channel region/inversion layer there needs to be be
some mechanism to remove these charge carriers in order for the channel to disappear and the MOSFET to switch off, this could either happen
over time if the switching frequency is very slow or if there is an external load/dummy resistor connected to the output which would drain this charge.
I was surprised this reasoning seems to be actually true as I connected a 100W incandescent lamp at the out output as load and get the MOSFET to switch up of 10KHz
with reasonable fall times. I guessed with the lower section of the bridge active the pull down would also become fast as there was an active
element(the lower MOSFET) pulling the output low dissipating the charge accumulated making up the channel region.

3) With the complete bridge circuit where both lower and higher side of the bridge are connected I am still not seeing a square wave output.
I see a very strange signal output. Image attached. Infact there is thru conduction taking place across the bridge. This happens despite there
being sufficient delay between the pulses being used to trigger the lower and upper MOSFETs making up the bridge. This is further confirmed
as I have safety fuses connected to the supply rail which blow up confirming a thru conduction! In fact I managed to destroy one set of MOSFETs
even before the usual glass cartridge fuse could react!!




Could any one give me some inputs/ suggestions where to look for the problem?
Any help would be highly appreciated.

Regards
Asimov

How do you measure the gate driver voltages, e.g. with a differential probe? How can you be sure that the waveforms are real?

I am suspecting that all the circuitry driving the upper FET is getting " blow through" due to the fact that their GND lines have 200V pulses on them and is actually the main load if the output load is only 50 pF.
Frannk

It's more usual to use a push pull drive for these apps and frequencies as then the mosfets can be driven properly, we have done similar in the past for small mass spectrometry "sniffing" devices...

See fig 30 page 16 of the u-semi pdf....

Even more than regular MOSFETs, RF MOSFETs will need RF kind of wiring. The circuit shown in the photo is apparently far from RF suitable layout. Showing a bottom side photo would clarify things.

Thanks every one for giving their inputs.
Answering all the questions and suggestions my answer to the
concerns are as follows
FVM: "How do you measure the gate driver voltages, e.g. with a differential probe? How can you be sure that the waveforms are real?"
Answer: I don't have access to differential probes, But in my case the 1:1 transformer and individual isolated gate supplies provided
isolation between the power supplies and the oscilloscope. Hence I hooked up the usual tektronix 1/10X probe P2220 between
the MOSFET gate and source and measured the waveform. While writing this reply I just came up with the idea of putting a parallel
dummy resistive load across the gate and then measure the gate waveform again to ensure they are genuine waveform rather than
noisy voltage pickup by oscilloscope probes. I am assuming noise voltages don't have sufficient current driving capability when one
puts the dummy low impedance loads.
Question 2 FvM: "Even more than regular MOSFETs, RF MOSFETs will need RF kind of wiring. The circuit shown in the photo is apparently far from RF suitable layout. Showing a bottom side photo would
clarify things." I will put up the PCB schematic in this post. This is an eagle file. I have tried to keep traces short and wide to have low inductance, had to keep a few jumper in the gate
driving signal as in some cases one needs to put small value resistors or bead inductor to suppress the gate ringing(https://www.fairchildsemi.com/application-notes/AN/AN-9005.pdf).
The ground plane with lot of stitched vias is advisable which I couldn't fully meet.

chuckey: True the high side MOSFET seems to have burnt up(shorted out) followed by low side MOSFET as the the two MOSFETs are alternatively switched. But I think its not a problem
related to the high side Gate being at a very high voltage(+200) with respect to the lowest potential point of the bridge as for avoiding this situation an isolated power supply
was used to power the gate driver circuit, ie: Vgs remained within the specified limit as the gate driver circuit is connected between the upper MOSFET gate and source.
Just that the upper side MOSFET seemed to turn on quickly on the rising gate pulse(as expected) but continues to remain on for a long period of time despite the gate pulse
is made low (possibly the charge carries taking a long time to recombine there by turning of the MOSFET). This is not a problem for low frequency 100 Hz but at 100 KHz it become s
problem. Also putting a resisitive load at the bridge out helps speeding up by quickly bleeding stored charge in the channel(my conclusion based on observation).

Orson Cart : Thanks for your input. I will re look at the section you have mentioned.

Attaching the eagle file for PCB layout.

You say that you access the gate voltage with a standrad passive oscilloscope probe. This means that either the oscilloscope or the complete circuit power supply most be floating. Large ground currents during switching transients caused by unavoidable circuit capacitances must be expected to ruin the measurement results. I won't trust it at all.

The fact that the main PCB topside has nearly no copper shows that there's much room left for reasonable ground wiring.

Hey Asimov,

While your solution is an order of magnitude more powerful than anything I've created/needed, here's a reference that offered me some inspiration when I needed to drive capacitive loads with a few hundred+ volts at MHz rates in our optics lab. I would have loved to have tried the vacuum tube topologies

https://arxiv.org/abs/physics/0506050

Good luck - what awesomely beastly MOSFETs!

I just realized I hadn't put the image for of the back side of the Board. I thought I had put it in the first post.

- - - Updated - - -

FvM said:

You say that you access the gate voltage with a standard passive oscilloscope probe. This means that either the oscilloscope or the complete circuit power supply most be floating. Large ground currents during switching transients caused by unavoidable circuit capacitances must be expected to ruin the measurement results. I won't trust it at all.

The fact that the main PCB topside has nearly no copper shows that there's much room left for reasonable ground wiring.

Click to expand...

Yes the power supply is floating but the scope wasn't. Thanks for the input regarding the usual probes not being good. Apart from the
differential probes is there an alternative means of doing gate measurement. If you check the fairchild application note they too seem to
be using a usual probe with a spring type ground conductor rather than the usual probe with the separate ground cable, I used similar way
to make the measurement, but that is just meant to improve the noise performance.

Another option would be to use both the channel of the and do a channel_A - channel_B trace. Would that be helpful?

I've been watching the IXYS "RF FETs" for a while. Back then their documentation was very scarce and the driver ICs weren't available. Then eGaN FETs came out and blew these out of the water. If I were attempting the same project I'd try these, but you're probably too far along to change horses now.

To properly measure the gate voltage without differential probes, you should use two single ended probes and subtract their traces. To ensure the results are accurate, the probes should have the exact same ground point, using spring/pigtail ground leads as short as possible, right at the FET source. If you use the probes on the exact same signal, then you should get two identical traces. If you don't, then your results are not going to be accurate.

I am wondering if a better approach to this whole problem might be to generate some high voltage 1Mhz sine waves, and do some serious voltage clipping right at the load.

And I agree with Thylacine1975, tube type technology may be a lot more applicable to this.

I once used a microwave oven transformer with its voltage doubling rectifier to power a large transmitter tube, which was continuously driven at 3Mhz as a plasma supply.
It was a real red neck contraption, but it also worked amazingly well for what it was.

50 pF load isn't particularly high for a fast MOSFET switcher, similar drivers are build since decades and are commercially available from specialized manufacturers. Reactive power of the present application is in a few watts range, so it won't need particularly big transistors.

I remember that HP made tube based high voltage pulse generators at least til the 80th, but I don't believe that's it's necessary to refer to this technology for main stream applications.

A critical parameter in many high voltage pulser used for mass spectrometry and similar applications is rise/fall time, I didn't yet hear a specification.

Solid state transistor based devices are available since 1990. In fact I managed to find the manual of a device by DEI now a subsidiary of IXYS. Interestingly this manual has the schematic at the last page.Looking at the schematic it seemed I was working in the right direction and using right components.


I am attaching the manual kindly look at the last page if interested.
https://ixapps.ixys.com/DataSheet/hv1000_manual.pdf

Would request the moderator to confirm if its alright to put this manual as it is available at IXYS website.

Looking at the schematic it seemed I was working in the right direction and using right components.

Click to expand...

I basically agree. But the schematic doesn't tell much about circuit layout. And you should consider that implementing a push-pull switch is a bit harder than the single ended HV1000 design.

You can IMPROVE scope pictures with rise times < 300ns using inductive ground wire on probes. Either remove tip and gnd lead and create 2 pins <1 cm apart, one being ground using 10:1 or two matched 10:1probes in A - B mode giving a flat line on same test point or better yet, SMD divider to 50 to SMA Coax terminated at scope with 50R BNC with V*2 factor from impedance match loss.

Low inductance lines means Litz wire, braid or wide tracks with low L/W ratio. Low impedance tracks means ground signal between tracks with stripline design or microstrip with ground plane with LC distributed.

Reverse body diode should be Low current , low Trr type with high conductance in forward or better Si-C type.

I like the MOT solution which is not very efficient but handles arcs smoothly with Klystron. With plasma's very low negative resistance, saturated MOT can regulate secondary current limits well vs a stepup transformer. MW Arc furnace transformers are designed with relatively high transfer impedance for inverse low Sh.Cct. current ratios.

Try to measure cross conduction problems that will blow one Mosfet and create a guaranteed deadtime worst case load of 0.5us. Or so...with faster turn-off times. Beware XOR gates and opto's are asymmetric in propagation delay which affects deadtime or lack of one as voltage is raised.

If you are following a proven design, then the differences must be in the switch, magnetic design or layout and probe techniques or all the above. Verify each component does as expected with accurate timing on scope.

Photo below shows 50KV partial discharge scaled down using long coax with 50Ohm termination with 1ns arc risetime recorded.

asimov_18 said:

Solid state transistor based devices are available since 1990.

Click to expand...

Very true, but semiconductors are still not always the easiest, simplest, or lowest cost path for some applications.

FvM said:

I basically agree. But the schematic doesn't tell much about circuit layout. And you should consider that implementing a push-pull switch is a bit harder than the single ended HV1000 design.

Click to expand...

This is where experience and inputs from forums come handy. Theoretically this is a simple textbook example which can be simulated.
But getting the actual circuit to work take much more than what colleges and university can teach. Everyone's help has been useful for me
to think and figure out what is possibly wrong with this design and layout.

Asimov

Can you tell us a bit more about the required rise and fall times for your experiment.
And about how the driver is impedance matched to the cable, and the cable to the load.

You appear to have no HVDC caps close to your power mosfets....? The gate drive turn off must be very low impedance at VHF and able to hold the gates down no matter the dV/dt on the fet drain....

Warspeed: "Can you tell us a bit more about the required rise and fall times for your experiment.
And about how the driver is impedance matched to the cable, and the cable to the load."

The rise time requirement are not very demanding about 100-200 nano sec is acceptable.

Orson Cart: "You appear to have no HVDC caps close to your power mosfets....? The gate drive turn off must be very low impedance at VHF and able to hold the gates down no matter the dV/dt on the fet drain...."

If you notice the first set of image, I have two x2 rating polypropylene caps on the top and two Electrolytic capacitor on the top side about 2 cm from the MOSFETs.
Could you re phrase the other bit relating to dV/dt . Essentially this is what is not happening.

I am putting this new scope image. This is just for the high side MOSFET being switched by 70 KHz signal The supply voltage is about 200V. If you notice the
MOSFET turns on multiple times and doesn't remain steadily on. I see the gate drive output too unstable. I was of the opinion that one the gate capacitance
is charged the gate driver would not be supplying any active current to gate other wise there shouldn't be a dip in either the gate driver waveform or the MOSFET output wave form.

Just to add a little more information I am powering the gate griver chip from a 12v supply (12V 7 Amp gel acid battery) to make it isolated and a low impedance source.