high stability LDO with fast transient response

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hi sir,
1)what is the advantage to use inductor based feed back in LDO?will it to DC voltage while doing AC analysis?
2)In design some MOSFETs scaled with exact 0.35um length and some MOSFETs scaled with multiple of 0.35um.How it will effect to our design?(iam using 0.35 CMOS technology)
Thanq
 

Use inductor in feedback for AC simulation?. If yes, it is used to remain DC feedback loop and break AC feedback loop.
Yes, AC analysis needs DC operating point.
Imagine different DC operating point will lead to different AC characteristic.
L will affect output resistance.
 
Hi sir ,there is a small doubt on MOSFET,0.35um CMOS technology:
1)what is the result value should be for [Vgs-Vds]?(if it is N-MOS)
2)Number of P-MOS 4 terminal devices connected in series , all substrate of mosfets needs to short with source or Vdd? How it will effect?Which one is prefarable to my base paper?
3)How to avoid threshold variation in my circuit (figure 3,base paper).I could't able to get all mosfets in saturation region?
4)What are the precautions i need to take for getting all MOSFET's in saturation region in
my design(fig 3,base paper)?
Thanq
 

1） Vgs-Vds? it depends operating point that the circuit works.
2) PMOS's body can be connected to source or Vdd according the circuit design requirement. It might lead to Vth increase if the body voltage is not equal to source voltage. It is called body effect that can be found for details in any basic analog circuit design book.
3) Threshold variation is mainly caused by process controlling. Pls found good process for smaller vth variation.
4) MOSFET working under linear region might lead to gain decrease.
 

Hi sir,
1)Margin values of Vds in saturation condition?Give some explanation sir?
2)please send TSMC 180nm CMOS technolgy model parameters.
Thanq...
 

1) typical 0.2V for Vdsat is OK.
2) Process file I got is confidential. I am sorry.
 
hi sir, i have designed LDO.Target with 100mA load current.But i have reached up to 25mA.I could't able to drive more load.My opamp gain is 80dB.70 degrees phase shift.Using 180nm CMOS technology.I could't find what's the problem.Constant Gm Bias circuit designed with input current 1.2uA.I could't able to drive more load than 25mA.
My design regulated with 1.8v.I regulated 1.8v with out load.Please find my problem.
Thanq
 

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What's the supply voltage for 100mA? Driving capability is limited by power PMOS size? If so pls increase its width.
 

Hi sir,
I have designed LDO with supply 3v.
Does't work my design with supply 3v when the load 100mA??
Iam using 180nm CMOS Technology,how much supply is sufficient for driving
100mA load?(Need to regulate 1.8v and dropout is 150mV).In DC analysis i sweep from 2v to 4v.
I already changed PMOS width up to W/L is 50000um/0.3um.If increase more width of PMOS,output voltage is slightly incresing (like 1.4333v to 1.4345v)
I regulated voltage 1.65v, up to 30mA load current only.
Thanq..
leo_o2 said:
What's the supply voltage for 100mA? Driving capability is limited by power PMOS size? If so pls increase its width.
Click to expand...
 

W/L=50000um/0.3um should be enough. Pls check the gate voltage of power PMOS when it can't drive 100mA. If it is close to ground, your model or netlist should have problem.
 

Hi sir,
In LDO design i have used reference voltage as DC voltage source(1.25v),instead of design bandgap circuit.Will my design properly work at typical conditions?

---------- Post added at 17:40 ---------- Previous post was at 17:25 ----------

Hi sir,
1)How i will get conclude my model file is correct or not?
2)At Pass transistor gate potential i got 2mv,if i increase width(10000u/0.18u) of pass transistor.I could't find why my opamp output can't provide sufficient potential to pass transistor gate terminal.
3)I have designed constant Gm bias circuit with 1uA input current and biased to opAmp.Will it sufficient regulate 1.8v@100mA load current??
 

Sir,Please refer the attached file
 

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Let's just consider Power PMOS. In your simulation, Vg=2mV, Vs=3V. So Vgs=~-3V.
When Vd=1.8V and W/L=50000u/0.3u, it can't output 100mA. It is not reasonable. So the PMOS model is wrong.

 
Hi sir, i have designed LDO with 100mA load. I have 90dB gain and 110degree phase margin. When i checked without load(0 mA) i got 65dB and poor phase margin 6degree. I could't find whats the problem.
 

That's quite normal: With zero load, the resistive part of the output impedance (ro of your output PMOS only, in this case) is maximum, hence the dominant (output) pole moves to lower frequencies and "eats up" your gain & phase margin.

If you can afford, add 1 or a few milliAmps of base load.
 

Something strange: lower gain @ 0mA than 100mA. Ususally gain @ 0mA is larger.
And I agree with erikl for phase margin.
raghuvlsi said:
Hi sir, i have designed LDO with 100mA load. I have 90dB gain and 110degree phase margin. When i checked without load(0 mA) i got 65dB and poor phase margin 6degree. I could't find whats the problem.
Click to expand...
 
leo_o2 said:
Something strange: lower gain @ 0mA than 100mA. Ususally gain @ 0mA is larger.
Click to expand...
This depends on the measurement frequency: You are probably right for very low frequencies, but e.g. @ 100Hz the gain curve could already show its 20dB/decade decline (in the zero load case).
 

Yes. I thought of DC gain.
 

Right: (open loop) DC gain should stay high. Concerns only very slow input voltage changes.
 

Hi sir, i have designed LDO with regulated voltage 2.5V with supply 3V. I sweep 2.7V to 4V and did DC analysis(without load condition) ,the output value is incresing from 2.5 to 2.582. At input 2.7V, output is 2.5V and input 4V, output is 2.58V. How can i regulate the design properly?
Thanq,
 

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