High speed signal coming from one domain to another

[sun_ray]

Suppose a one bit signal is coming from one clock domain and is necessary to be transferred to another clock domain. The one bit signal may change in frequently and even once in every two/one clock cycle. How can this signal be transferred? Can there be any handshake mechanism to transfer this one bit signal to another domain?

Regards

 

[barry]

You will need to use a synchronizer. The simplest approach is the two-flip-flop synchronizer.

 

[sun_ray]

Barry

For the problem I provided your solution will not work.

 

[barry]

Can you restate your problem? I'm not sure what you mean by "The one bit signal may change in frequently and even once in every two/one clock cycle."

 

[sun_ray]

Can you restate your problem? I'm not sure what you mean by "The one bit signal may change in frequently and even once in every two/one clock cycle."

The description of the signal is as folllows

(i) It has width of one bit. So it is a one bit signal.
(ii) It is high speed. So the signal changes quite frequently.
(iii) The signal may be changing once in two clock cycles in the source clock domain. So when the signal is originated in source clock domain the signal can be changing once in two clock cycles in the source clock domain.

Now you need to transfer this signal to another clock domain and this another domain may have any frequency value.

Is it clear now?

Regards,

 

[barry]

You can stretch this signal so that it always will be wider than the period of the destination clock, ensuring that it will always get captured in the destination domain. Or, you can use the edge of this signal to drive the clock input of a ff, and reset the ff with a signal from the destination domain. You need to figure out exactly what you are trying to do, and ensure that you are avoiding metastability.

 

[sun_ray]

You can stretch this signal so that it always will be wider than the period of the destination clock, ensuring that it will always get captured in the destination domain. Or, you can use the edge of this signal to drive the clock input of a ff, and reset the ff with a signal from the destination domain. You need to figure out exactly what you are trying to do, and ensure that you are avoiding metastability.

But here the signal is changing quiet frequently and so above methodology will not work as there is not sufficient gap between two clock cycles for my signal.

 

[binliu]

There are different scenarios for when the clock frequency is slower than or faster than your source clk freq.

have one solution for all scenarios are tough. I remember I did some latch mechanism for handshakes between two clock domain. it is not a simple async fifo solution, especially fifo will add unnecessary delay....

Actually, while i am typing... i am thinking... if your signal is toggling at faster freq from source clk all the time, there is no way you can preserve the info by try to catching it with a low freq clk, am I right?

Maybe you can make your situation more specifically.

Thanks

The description of the signal is as folllows

(i) It has width of one bit. So it is a one bit signal.
(ii) It is high speed. So the signal changes quite frequently.
(iii) The signal may be changing once in two clock cycles in the source clock domain. So when the signal is originated in source clock domain the signal can be changing once in two clock cycles in the source clock domain.

Now you need to transfer this signal to another clock domain and this another domain may have any frequency value.

Is it clear now?

Regards,

 

[barry]

Binliu is absolutely right. You want to violate the laws of nature; you can't convert a 10 MHz data stream to a 5 MHz stream. However, if this data is of a burst nature where it's AVERAGE rate is less than the slow clock domain, you ca muse a FIFO approach

 

[sun_ray]

binliu

A signal cannot toggle at faster freq from source clk all the time. So my signal is slower than source clock. So I provided the specification that the signal toggle once in every two clocks.

barry

There is no violation of nature here. How are you defining your average rate when you says "However, if this data is of a burst nature where it's AVERAGE rate is less than the slow clock domain, you ca muse a FIFO approach"? What are the conditions to be satisfied for this average rate to transfer data safely?

 

[binliu]

What about the other side? does the clk freq has a set relationship with the source or not？and how many bits the other side take each time?

I agree with Barry, sounds like a fifo solution..

binliu

A signal cannot toggle at faster freq from source clk all the time. So my signal is slower than source clock. So I provided the specification that the signal toggle once in every two clocks.

barry

There is no violation of nature here. How are you defining your average rate when you says "However, if this data is of a burst nature where it's AVERAGE rate is less than the slow clock domain, you ca muse a FIFO approach"? What are the conditions to be satisfied for this average rate to transfer data safely?

 

[barry]

Sun ray, you said your signal "MAY change", you didn't say it would ALWAYS change once every two clocks. I think if that's the case then you can use a two-flip-flop synchronizer. However, if your destination clock is EXACTLY 1/2 the frequency of your source clock, there may be a problem.

That was a typo in my last message (I was using my smart phone, which is not so easy to type on) it should have said "you can use a FIFO". By average rate I mean a situation, for example, where you've got bursts of 10 bits at 100 MHz that occur once every microsecond. The BURST rate is 100MHz, but your AVERAGE rate is 10bits/microsecond =10MHz rate

 

[sun_ray]

barry

Let me again state about my signal for you. My signal is an arbitrary signal which can come once in two clock cycles for the first 8 clock cycles, then it can come two in next ten clock cycles, then it comes as one in next 10 clock cycles. It is an arbitrary signal which can change once in two clock cycle and even once in 5 clock cycles and once in ten clock cycle. Can you please provide a solution now?

Second question from you answer:

What is your answer of the solution if the signal always change once in two clock cycles? You wrote that two stage synchronizer will not work here because the destination clock may can be EXACTLY 1/2 the frequency of your source clock.

Regards