High speed pulse train counter using FPGA

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simbaliya

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Hi Pros,

I need to count a TTL level high speed pulse train, rise time 1ns, fall time 1ns, pulse width 10ns, period 20ns.

I see that a lot of MCU input are not fast enough to capture such a high speed pulse, even some 24bit asynchronous counter, the parallel output is only the last 8bit, means the lower 16 bit information is missing.

I wonder, normally how this high speed pulse train is counted with high resolution(at least 18 bit resolution).

I heard FPGA is a possible option, can somebody advise why FPGA is an option?
 

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Many FPGAs no longer have TTL-compatible levels
on input buffers. You might need something like
a low voltage CMOS level shifting buffer to knock
voltage down and stiffen up the edges.
 

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dick_freebird said:
Many FPGAs no longer have TTL-compatible levels
on input buffers. You might need something like
a low voltage CMOS level shifting buffer to knock
voltage down and stiffen up the edges.
Click to expand...
Most FPGAs do, in fact, have LVTTL inputs. OP has already said he’s got 1ns rise time, no further “stiffening” is needed. At worst, maybe a voltage divider would be needed.
 

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Hi,

20ns period equals to 50MHz.

So the MSB of an 8 bit synchronous counter will toggle with about 400kHz.

It usually makes no sense to read out a 18 bit counter during 50MHz counting, thus I recommend to use some pulse gating.
Count the pulses for a given period of time, then read out the value when counting is stopped.
Or you may use some output DFF to freeze a counter value ... but counter still is counting on.

I guess it's a good idea to tell us more about your application. .. to get useful assistance.

****
simbaliya said:
Hi, can you tell me, what is the hardware difference, to make FPGA faster than normal MCU? Thanks
Click to expand...
An MCU is a complex logic device .. with a lot of gates. Even gates in series, which causes the delay of each gate to be added up.
So when you say an FPGA is faster than an MCU you compare apples with oranges.
If you want to compare both you need to implement the full (identical) logic of the MCU in question into the FPGA ... then compare them.
--> The speed of a single gate is determined by it's technology .. mainly structure sizes, voltage levels....
--> The speed of a circuit additionally is determined by the logic complexity.

Klaus
 

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Thanks for your valuable reply.

My application is to read out the Hamamatsu Photo-Multiplier Tube Module output, the output is a TTL pulse with 20ns period, you can find the datasheet of the PMT below

The PMT will capture some super low level light in a small amount of time (1s e.g.), will then convert the light energy during this time to a number of high speed pulse as mentioned above. My job is to find a IC/Device to calculate the number of pulse, of course Hamamatsu does providing pulse counting unit with USB interface, but it is expensive and big in term of size, so I am wondering if any MCU of FPGA can do the work.

I need to count very accurately since the PMT need dark calibration, in which case the number of pulse can be in the range of a few hundred, thus those 24 bit asynchronous counter with only the last 8 bit output is not an option.
 

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Hi,

What is your idea?
Let's say you have an MCU which can count up to 50MHz. (I'm sure there are some).
What is your signal flow, the timing, the processing?

*******
A rather simple solution:
Use a ESP32. It can count with input frequency up to 40MHz.
If this is too slow, then use a 74AUP1G74 as 2:1 frequency divider in front of it.

Klaus
 

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simbaliya said:
Hi, can you tell me, what is the hardware difference, to make FPGA faster than normal MCU? Thanks
Click to expand...
Hardware execution of a "baked in" algorithm/architecture rather than cycle by cycle code execution on general purpose architecture.
 

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I'm not sure I quite understand what's going on here. You say "The PMT will capture some super low level light in a small amount of time (1s e.g.), will then convert the light energy during this time to a number of high speed pulse as mentioned above". So, you think that it samples for 1 second, and then bursts out a proportional number of pulses at 50MHz?

The way I'm reading the low-information data sheet (and I could be very wrong), is that it puts out a continuous stream of pulses, and the frequency of those pulses is proportional to the light intensity.

Can someone correct me?
 

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The 8-bit timer resolution is usually extended by counting the overflows, e.g. by an interupt routine. The information is not necessarily lost, you need to read the controller datasheet thoroughly and understand its capabilities.

I presume that at least some higher performance controllers can count at 50 MHz, nevertheless it can be reasonable to use a FPGA for the job.
 

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