High Speed OpAmp Design for SAR ADC

[vladimir1984]

high speed charge redistribution adc

Hi everybody!

I design a single ended 12-bit charge redistribution SAR ADC. And now I meet the problem with a big influence of MOS offsets to the resolution of ADC. As the main component in SAR ADC is comparator, which determines, in principle, the overall accuracy of circuit, the normal offset of 10mV of MOS in my 0.6µm CMOS technology limits the resolutiion to 8 bit.
The offset of my usual OpAmp is about 140µV by typical simulation.
So for 12 bit SAR ADC with 100KS/sec throughput rate I need the OpAmp with the gain no less 83dB at 1.2MHz. No I have OpAmp with 83dB only at 100Hz.
Can anyone provide me some advise or link or example of design high gain OpAmp at frequency more than 1MHz.
Why I use the OpAmp as the comparator in SAR ADC? The reason is following, I need to perform offset cancellation, and I can not make it with usuall comparator, which is not unity gain stable.
Maybe there is special technique of offset cancellation with the usuall comparator? Please share your knowledges in this field.

Thanks for any help!

 

[maxwellequ]

successive approximation adc resolution mismatch

First, I advise you to read papers about SAR ADCs with specifications similar to your's (I'm sure you can find this).

The comparator to use should be a "latched comparator", using positive feedback. The offset voltage can be reduced by using pre-amplifier stages before the latched comparator, where offset cancellation can be performed (OOS/IOS - see Razavi's book on data converters for example).

Finally, why do you need a small offset voltage for the comparator in a SAR ADC ? Is the offset voltage of the ADC an important specification ?

Regards

 

[vladimir1984]

cause of offset in sar adc

Thank you for answer.
The reason of small offset comparator it following. The offset of the comparator (or threshold voltage, I think it is similar) it is the difference of input voltages of comparator which can comparator resolve. When I have a 12 bit SAR ADC with Vref=4V, it's means that the quantization step Vlsb=Vref/2^N=0.97mV. So, if I have comparator which can resolve the difference only greater than 10mv for example, I'll have a huge INL and DNL errors.
Yeah, preamplifier must help to solve this problem

 

[maxwellequ]

sar adc silicon issues

vladimir1984,

For some reason, that is a usual misconception in the design of SAR ADCs. One of these days I would like to understand why ...

The offset voltage of the comparator will affect the code transition levels of he ADC (i.e. it will shift, from the ideal value, the input voltage at which the transition between the consecutive output codes occurs). But, and this is very important, it will shift ALL the code transition levels by the SAME amount (if you think a bit about that, you'll see that I'm right.)

So the offset voltage of the comparator introduces an offset voltage on the overall transfer function of the ADC - ADC offset voltage. It does NOT cause linearity problems. So you only have to guarantee low comparator offset if the ADC offset voltage is an important parameter for your application.

Regards

 

[vladimir1984]

mimize mismatch in sar adc

Thank you a lot. I was wrong.
I try to design a latched comparator, with a regenerative latch.
And I should to precise the specification requirements.

 

[maplefire]

op design for adc

your comparator must reach 12bit resolution,or your SAR A/D can't be 12bit.
usually autozero or offset cancelling are used in these comparator.

 

[maxwellequ]

12 sar cdac

maplefire,

You are not right. And I've designed a few 12-bit SAR ADCs that worked correctly, in case you're wondering.
I advise you to think a bit before starting to state wrong things, that will surely not help other people.

Regards.

 

[vladimir1984]

transistion level in adc

Dear maxwellequ

As I know you have some experience of design successful SAR ADC. May be you can give me some advice concerning the architecture of SAR ADC. What combination is more better for the DAC, only with caps, or hybrid caps and resistors. Now I have problems, I made analysis of deviation of capacitance at 60 MC runs and 2 corners over temperature -40 to 150. The result is very worse, 25% for CpolyCpolyG.
It is almost imposible to achieve good linearity with such mismatch. Because my task is to design simple single-ended 12-bit charge redistribution SAR ADC without caps calibrating techniques. Did you used it?

Best regards

 

[incanada1]

sar adc ic design and simulation

my 8Bits. SAR ADC is 0.35um,which could tell the input deifference at low as 10uV to 200mV.using multi stage preamplifier and regenerative latch as comparator,
oos,ios is not used.-3dB bandwidth is around 10Mhz

 

[maplefire]

adc op design

maxwellequ:

if your comparator have only 10 bit resulotion,
how can you guarantee your SAR to work correctly
with a 12 bit input?

there are a lot of missing codes with a input higher than 10 bit resolution.

Is your SAR a real chip or just a simulation?

maybe you don't care missing code at all.

 

[bastos4321]

12 bit sar adc

maxwellequ:

if your comparator have only 10 bit resulotion,
how can you guarantee your SAR to work correctly
with a 12 bit input?

there are a lot of missing codes with a input higher than 10 bit resolution.

Is your SAR a real chip or just a simulation?

maybe you don't care missing code at all.

Dear Maplefire, I know the work of maxwellequ and it's not simulation but real silicon proff at 12 bit level.

Bastos

 

[maxwellequ]

sar adc transfer function

Maplefie,

Imagine a SAR ADC, where before the comparator there is a switched capacitor which samples the input voltage, and the, successively connects to the reference voltages generated by a resistive ladder, to find the reference voltage nearer the sample input.
Let's take the example of a 12bit SAR ADC with a 2 V full scale range - LSB=2/4096=0.488 mV, which has a resistive ladder that generates the 4095 reference voltages (usually there is some kind of segmentation, but let's consider this simpler case). Finally, consider that the comparator has an offset voltage of 5 mV (i.e. more than 10 LSBs).

Now, let's answer the question: "What is the input voltage voltage value that makes the output code of the SAR ADC change from 0 to 1?"
If there was no offset voltage it would be vi=LSB=0.488mV, but due to the offset it is vi=5.488mV -> more than 10 LSBs away.

No you're saying: "See, told you so...". Well, hold on a bit. And what about the question: "What is the input voltage voltage value that makes the output code of the sar ADC change from 2047 to 2048?". If there was no offset voltage it would be vi=2048xLSB=1V, but due to the offset voltage the transition occurs at vi=1.005 mV -> again more than 10 LSBs away...

So, due to the offset voltage of the comparator, we have a large deviation in both the code transition levels considered above. The point is that, although the deviation is large, IT IS EXACTLY THE SAME FOR THE TWO CODES.... and for ANY other output code that you may consider.
This means that the offset of the comparator shifts the FULL transfer function of the ADC - i.e. causes the ADC to have an offset - but DOES NOT cause nonlinearities (for this to happen the offset of the comparator would have to cause code dependent deviations, which does not happen).

In a SAR ADC, INL and DNL are caused by the mismatches between the elements of the DAC (resistive ladder in the example above)

Regards.

PS1: Silicon proven, no missing codes, decent INL and DNL.
PS2: Thanks Bastos.

 

[jordan76]

sar charge offset voltage

Hi maxwellequ,

"In a SAR ADC, INL and DNL are caused by the mismatches between the elements of the DAC (resistive ladder in the example above) "

Would you share your experiences and knowledge of what methods you are using to minimize the mismatches between the resistive ladder? Thanks!

regards,
jordan76

 

[maxwellequ]

n bit sar adc, rdac,cdac

The area of the resistors must be obtained from Monte-Carlo simulations. Then follow the usual rules for good analog layout (same orientation, use dummies, ...)

 

[captab]

high speed adc 74hc

maxwellequ,

I am working on 10 bit SAR ADC with 4MSPS/Bits. In fact I have the first set of postsilicon INL/DNL results for the same which are not in spec.From the results, the INL is way out of the spec with shift in the INL for the first & last 64 codes. The ADC is hybrid with 4bit MSB RDAC & 6 Bit LSB CDAC. Can you please help me to figure out that is it the problem related only to the RDAC or CDAC & comparator.

Regards,
captab

 

[maxwellequ]

the working of saradc using cdac+rdac

captab,

It seems that you have INL problems in the codes obtained by the CDAC, when it connects to the terminals of the first and last resistors. I advise you to check it you don't have IR drop problems in those connections.

Regards