Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

High speed buffer design

Status
Not open for further replies.

suria3

Full Member level 5
Full Member level 5
Joined
Mar 5, 2004
Messages
300
Helped
17
Reputation
34
Reaction score
5
Trophy points
1,298
Activity points
3,028
Hi people,

In the high speed receiver design, i'm trying to isolate a large RC low pass filter filter that feedback to the dc offset extractor circuit from effecting the circuit bandwidth and loading. Right, now i 'm utilizing the Ft-Doubler architecture as a buffer to isolate this load, is there any other options i can do or any other design of high speed buffer besides the mentioned ft-doubler.

Thanks,
Suria3.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top