High-Level Synthesis (HLS) vs RTL for ASIC flow

[oAwad]

Hi,

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level netlist, or is there a specific HLS synthesis tool? and how efficient is ASIC flow for HLS compared to RTL in terms of clock freq., area, and power? Does HLS C/C++ development really save the design time compared to RTL ?

Thanks

 

[ThisIsNotSam]

Hi,

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level netlist, or is there a specific HLS synthesis tool? and how efficient is ASIC flow for HLS compared to RTL in terms of clock freq., area, and power? Does HLS C/C++ development really save the design time compared to RTL ?

Thanks

HLS has found its space in fpga prototyping and in some application domains, but it is not a staple in ASIC design. When it works, it does save time, of course.

DC can't do HLS.
Generally speaking, hls will produce an inferior solution than a properly designed hand written code.

 

[weetabixharry]

DC can't do HLS.

However, HLS tools generally generate RTL code (i.e. you input C/C++ and it spits out VHDL/Verilog), which can then be compiled by DC.

Generally speaking, hls will produce an inferior solution than a properly designed hand written code.

This was almost always true a few years ago. However, HLS tools are genuinely getting better. The case studies (based on - admittedly - carefully selected tasks, well-suited to HLS) are increasingly showing that HLS produces better solutions than your average design engineer. And I don't just mean much faster development time, I mean smaller area and superior timing performance.

In my opinion, it will likely be one of those things where it will be better for some tasks and worse for others. Part of the challenge for design engineers will be to know which is which.

 

[javierh.santiago]

However, HLS tools generally generate RTL code (i.e. you input C/C++ and it spits out VHDL/Verilog), which can then be compiled by DC.

In my opinion, it will likely be one of those things where it will be better for some tasks and worse for others. Part of the challenge for design engineers will be to know which is which.

Completely agree with that. In my own experience, HLS is pretty good with datapaths in terms of design exploration as you can easily trade-off performance and area. For instance, re-using arithmethic units to process a given application.