High Impedance in Verilog-A

bajji_boy · Jul 1, 2008

Hi everyone

I was wondering if there was a way to model a floating node in verilog-a. I was actually working on a simple model for a switch (including its on-resistance). What is wish to do is to 'float' the output node when the switch is off...

Cheers
Nihit

solidstate · Jul 2, 2008

You can do two things, either a large Roff or open switch. I prefer the first for simulation converging.

So when you have

V(in,out) <+ I(in,out) * Ron;

in the on state, you would have either

V(in,out) <+ I(in,out) * Roff;

or

I(in,out) <+ 0;

Hope this helps.

bajji_boy · Jul 2, 2008

Thanks for the response solidstate

I tried the latter, I(in, out) <+ 0, but as you guessed, it gave me convergence issues since V(out) was connected in a feedback loop.

I will be probably try the first model and get back to you...

Cheers

High Impedance in Verilog-A

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solidstate

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High Impedance in Verilog-A

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