"Hierarchical" instance naming in DC

[Ludwick]

Hi,

I am using Synopsys Design Compiler (Version B-2008.09) to create a Verilog file from a circuit specified in several VHDL files.

The top level circuit given in VHDL includes several shift registers:

entity cossma is

port(	
	input: in std_logic_vector(3 downto 0);
	clk: in std_logic;
	set_ff: in std_logic;
	set_ff_data : in std_logic_vector(63 downto 0);	
	output : out std_logic_vector(63 downto 0)
);
end cossma;  

architecture behv2 of cossma is 
	signal y : std_logic;
begin 
	y <= input(0) xor input(1) xor input(2) xor input(3);
	nlmisr01 : nlmisr PORT MAP (input => input, y => y, clk => clk, output => output(3 downto 0), 
					set_ff => set_ff, set_input => set_ff_data(3 downto 0));
	nlmisr02 : nlmisr PORT MAP (input => input, y => y, clk => clk, output => output(7 downto 4),
					set_ff => set_ff, set_input => set_ff_data(7 downto 4));

-- and so forth...

Each Shift-Register is defined as something like this, consisting of registers and gates:

entity nlmisr is

port(	
	input: in std_logic_vector(3 downto 0);
	y : in std_logic;
	clk: in std_logic;
	output : out std_logic_vector(3 downto 0);
	set_ff : in std_logic;
	set_input: in std_logic_vector(3 downto 0)
);
end nlmisr;  

architecture behv2 of nlmisr is 
	signal ff: std_logic_vector(3 downto 0) := "0000"; 

begin 
	proc1: process(clk)
	begin
		if (rising_edge(clk)) then
			if (set_ff = '1') then
				ff <= set_input;
			else
				ff <= (input(0) xor ff(2) xor (y or not ff(3)));
			end if;
		end if;
	end process;
	output <= ff;
end behv2;

When I use DC to create a Verilog file from the above VHDL files, I use a script containing the following lines:

...
remove_design -all

set verilogout_no_tri true
set verilogout_equation false
set verilogout_higher_designs_first false
set verilogout_show_unconnected_pins false

set bus_naming_style %s_%d
set_fix_multiple_port_nets -all -feedthroughs -outputs
define_name_rules verilog -remove_internal_net_bus -equal_ports_nets

remove_bus *
elaborate $CIRCUIT_ENTITY_NAME -library WORK -update
link
uniquify
remove_bus *

set_fix_multiple_port_nets -all -feedthroughs -outputs
define_name_rules verilog -remove_internal_net_bus -equal_ports_nets

check_design

compile -ungroup_all -map_effort medium -area_effort medium
change_name -h -rule verilog
write $CIRCUIT_ENTITY_NAME -format verilog -output $EXPORT_PATH$CIRCUIT_NAME\_syn.v

In the output Verilog file I get the registers belonging to the shift registers with a naming like this. I.e. I can tell which register belongs to which shift register:

  DFF_X1 nlmisr01_ff_reg_3 ( .D(nlmisr01_N10), .CK(clk), .Q(output_3), .QN(n25) );
  DFF_X1 nlmisr01_ff_reg_2 ( .D(nlmisr01_N9), .CK(clk), .Q(output_2), .QN(n73));
  DFF_X1 nlmisr01_ff_reg_1 ( .D(nlmisr01_N8), .CK(clk), .Q(output_1), .QN(n71));
  ...

The other gates, however, have a different naming. I.e. I cannot tell any more from which shift register they stem:

  NAND3_X1 U19 ( .A1(n84), .A2(n85), .A3(n86), .ZN(n83) );
  NAND2_X1 U20 ( .A1(n87), .A2(n26), .ZN(n85) );
  NAND2_X1 U21 ( .A1(n88), .A2(output_63), .ZN(n84) );

My question is, if there is a way to change the naming of DC such that the other gates too would have a naming like for example nlmisr01_NAND3_U19 ...? This is important to me, because we want to harden the design against failures in different parts.

Thanks a lot for reading this!

Cheers,
Ludwick

 

[kornukhin]

Use "ungroup -prefix" command for each design.
Don't use ungroup_all during compile. So at least you will keep hierarchy.
But I'm not sure about keeping prefix_names for logic gates during compile (DFFs keep their names).

 

[Ludwick]

Thanks a lot, your hint worked great!

I replaced

compile -ungroup_all -map_effort medium -area_effort medium

with

compile -map_effort medium -area_effort medium
ungroup nlmisr*

Then my verilog output gives me

NAND2_X1 nlmisr01_U39 ( .A1(set_ff_data_3), .A2(set_ff), .ZN(nlmisr01_n28) );
INV_X1 nlmisr01_U38 ( .A(input_0), .ZN(nlmisr01_n37) );
OR2_X1 nlmisr01_U37 ( .A1(nlmisr01_n37), .A2(output_2), .ZN(nlmisr01_n35) );
NAND2_X1 nlmisr01_U36 ( .A1(output_2), .A2(nlmisr01_n37), .ZN(nlmisr01_n36) );

and so forth!

Thanks again! You saved me the effort of writing an extra script which would be crawling through the circuit wire by wire to extract the hierarchy of the gates... :-D