Hierarchical extraction with Assura: "Conflict between symbol and ...."

Maybe I posted it before in the wrong section...

Hi everybody,

I'm trying to simulate the effects of my layout routing from the pads to the core of a mixed-signal ASIC.
My idea was to hierarchical extract the whole layout and then simulate the connection parasitics with the
subcells at schematic/functional level to make the process faster. (For some reasons the pads are few
millimeters away from the core and DC currents play an important role so I'd like to estimate the voltage drop)
I managed to do the extraction using Assura LVS with ?preserveParameters and QRC with HRCX and for every
subcell the option "+ netlist=none": looking at the hierachical tree of the extracted view everything looks fine
and the config view for the test bench is also created without any problem.
However when I try to netlist with ADE L (Spectre) I got for every subcell the following error:

Netlist Error: Conflict between symbol view and schematic view of instance "DIGITAL" in cell-view "ext_a_WORKBENCHES_NCG" "NCG_22um_Chip_rcx" "analog_extracted_RCH_array"

where DIGITAL is e.g. one of the subcells and ext_a_WORKBENCHES_NCG is the library created by HRCX, which contains "NCG_22um_Chip_rcx".
I checked all CDF information of all cells in the main library (WORKBENCHES_NCG) and didn't find any uncongruence as well as I tryed to repeat the same
procedure with a simpler circuit (inverter + routing + pad), but I cannot figure out where the problem could be.
Is there any way to look into the subcircuits definitions (term order and so on) that are create by HRCX/contained
in any extracted view?

I'll be gratefull for any hint or suggestion,
thanks in advance

Gabriel

I'd recommend the blackBox LVS - flat QRC-RCX flow.
Everything else would remain same. blackBox the cells - which you want functional/schematic.
To have blackBox working with LVS match, you may need to tweak around your LVS extract.rul to have blackBoxLayers, pinLayer etc.. so that you retain pin geometries of the blackBoxCells during LVS.

Hi Sat,

thank you very much for your reply!
As you thought I cannot get any LVS match - layout extracted pins of my subcells have different names than the schematic ones and I have actually no idea how i can get rid of it.
I tryed to understand how blackBoxLayers work reading the Assura's Developers Guide but I must say it's not so clear... :/
I though however, even if there is no match I could use flat QRC since it works with the schematic extracted netlist, doesn't it? So I've got a right analog_extracted view and in my testbench
I can create the desired config view. Netlisting is however still impossible: symbol's terminals don't match the cell view in the extracted view....