[SOLVED] Hierarchical block is unconnected

   module modified_vedic_multiplication(q1,u,q2);
   input [19:0] q1;
   input [19:0] u;
   output [19:0] q2;
   wire [31:0] d,g,temp1,temp2,temp3,e;
   wire [15:0] temp4;
   wire c1,c2,c3;
   wire [7:0] f;
   vedic_16bit y0 (q1[15:0],u[15:0],d[31:0]);
   vedic_16bit_modified m1 (u[15:0],q1[19:16],g[31:0]);
   vedic_16bit_modified m2 (q1[15:0],u[19:16],e[31:0]);
   vedic_4bit m15 (q1[19:16],u[19:16],f[7:0]);
   assign temp1 = {4'h0,d[31:16]};
   full_adder_32bit_reversible r0 (e[31:0],g[31:0],1'b0,temp2[31:0],c1);
   full_adder_32bit_reversible r1 (temp1[31:0],temp2[31:0],1'b0,temp3[31:0],c2);
   assign q2[11:0] = temp3[15:4];
   full_adder_16bit_reversible r2 (temp3[31:16],{8'b0,f[7:0]},1'b0,temp4[15:0],c3);
   assign q2[19:12] = temp4[7:0];
   endmodule

     module full_adder_16bit_reversible(a,b,cin,sum,carry);
     input [15:0] a,b;
     input cin;
     output [15:0] sum;
     output carry;
     wire c;
     full_adder_8bit_reversible a12 (a[7:0],b[7:0],cin,sum[7:0],c);
     full_adder_8bit_reversible a13 (a[15:8],b[15:8],c,sum[15:8],carry);
     endmodule

     module full_adder_8bit_reversible(a,b,cin,sum,carry);
     input [7:0] a,b;
     input cin;
     output [7:0] sum;
     output carry;
     wire c;
     full_adder_4bit_reversible a2 (a[3:0],b[3:0],cin,sum[3:0],c);
     full_adder_4bit_reversible a3  (a[7:4],b[7:4],c,sum[7:4],carry);
     endmodule