Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Hidden State of Ideal Sampler

Status
Not open for further replies.
N

neo

Member level 2
Member level 2
Joined
Aug 19, 2004
Messages
51
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
Beijing
Activity points
450
Do you guys know how to implement the ideal sampler by using verilog-a and donnot generate the hidden states so as not to upset the spectre-RF simulator?
Thanks a lot!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top