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Hi all,doubt about verilog task

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VLSImaniac

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Hi, can anyone tell me why we should not model synchronous logic in a task?
 

Hi,
A task can only be called from within a procedural block,which for synthesis means a sequential begin-end block.A begin-end block can only be inside an always statement which must contain posedge or negedge construct in the sensitivity list,in order to model synchronous logic.Since synthesis tools cannot suport nested edge-triggered constructs,a task cannot be used to model sync logic.(read it somewhere, correct me if I am wrong)
 

    VLSImaniac

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