Help with VerilogA in Cadence

[CHIPMUNK_kevin]

Hello,

I was trying to use verilogA to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error

Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only
process cellviews that have a valid .oa file. This file can be created by
either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by
opening and writing the text file in the Library Manager.

I am pretty sure the verilogA code is correct , because it is succeful in another computer , but in my computer I found it miss the data.dm and netlist.oa files . So I am not sure what is the problem is ?


I am fairly new in Cadence so any suggestion what I can i do to fix it?


thanks in advance

 

[pancho_hideboo]

Create new cell with correct procedure.